OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

anv: rename internal heaps

Browse Source 
Some of the names are a bit confusing. The main change is to introduce
the "indirect_" prefix.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25955>
This commit is contained in:
Lionel Landwerlin
2023-10-11 23:48:01 +03:00
committed by Marge Bot
parent f9753488ec
commit ed83d1415c
8 changed files with 102 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/intel/vulkan/anv_cmd_buffer.c
View File

@@ -153,8 +153,8 @@ anv_create_cmd_buffer(struct vk_command_pool *pool,
&device->dynamic_state_pool, 16384);
anv_state_stream_init(&cmd_buffer->general_state_stream,
&device->general_state_pool, 16384);
anv_state_stream_init(&cmd_buffer->push_descriptor_stream,
&device->push_descriptor_pool, 4096);
anv_state_stream_init(&cmd_buffer->indirect_push_descriptor_stream,
&device->indirect_push_descriptor_pool, 4096);
int success = u_vector_init_pow2(&cmd_buffer->dynamic_bos, 8,
sizeof(struct anv_bo *));
@@ -205,7 +205,7 @@ destroy_cmd_buffer(struct anv_cmd_buffer *cmd_buffer)
anv_state_stream_finish(&cmd_buffer->surface_state_stream);
anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
anv_state_stream_finish(&cmd_buffer->general_state_stream);
anv_state_stream_finish(&cmd_buffer->push_descriptor_stream);
anv_state_stream_finish(&cmd_buffer->indirect_push_descriptor_stream);
while (u_vector_length(&cmd_buffer->dynamic_bos) > 0) {
struct anv_bo **bo = u_vector_remove(&cmd_buffer->dynamic_bos);
@@ -270,9 +270,10 @@ reset_cmd_buffer(struct anv_cmd_buffer *cmd_buffer,
anv_state_stream_init(&cmd_buffer->general_state_stream,
&cmd_buffer->device->general_state_pool, 16384);
anv_state_stream_finish(&cmd_buffer->push_descriptor_stream);
anv_state_stream_init(&cmd_buffer->push_descriptor_stream,
&cmd_buffer->device->push_descriptor_pool, 4096);
anv_state_stream_finish(&cmd_buffer->indirect_push_descriptor_stream);
anv_state_stream_init(&cmd_buffer->indirect_push_descriptor_stream,
&cmd_buffer->device->indirect_push_descriptor_pool,
4096);
while (u_vector_length(&cmd_buffer->dynamic_bos) > 0) {
struct anv_bo **bo = u_vector_remove(&cmd_buffer->dynamic_bos);

4
src/intel/vulkan/anv_descriptor_set.c
View File

@@ -1567,10 +1567,10 @@ anv_push_descriptor_set_init(struct anv_cmd_buffer *cmd_buffer,
struct anv_physical_device *pdevice = cmd_buffer->device->physical;
struct anv_state_stream *push_stream =
pdevice->indirect_descriptors ?
&cmd_buffer->push_descriptor_stream :
&cmd_buffer->indirect_push_descriptor_stream :
&cmd_buffer->surface_state_stream;
uint64_t push_base_address = pdevice->indirect_descriptors ?
pdevice->va.push_descriptor_pool.addr :
pdevice->va.indirect_push_descriptor_pool.addr :
pdevice->va.internal_surface_state_pool.addr;
/* The previous buffer is either actively used by some GPU command (so

39
src/intel/vulkan/anv_device.c
View File

@@ -2957,7 +2957,8 @@ decode_get_bo(void *v_batch, bool ppgtt, uint64_t address)
return ret_bo;
if (get_bo_from_pool(&ret_bo, &device->internal_surface_state_pool.block_pool, address))
return ret_bo;
if (get_bo_from_pool(&ret_bo, &device->push_descriptor_pool.block_pool, address))
if (device->physical->indirect_descriptors &&
get_bo_from_pool(&ret_bo, &device->indirect_push_descriptor_pool.block_pool, address))
return ret_bo;
if (!device->cmd_buffer_being_decoded)
@@ -3226,9 +3227,15 @@ VkResult anv_CreateDevice(
device->physical->va.high_heap.addr,
device->physical->va.high_heap.size);
util_vma_heap_init(&device->vma_desc,
device->physical->va.descriptor_pool.addr,
device->physical->va.descriptor_pool.size);
if (device->physical->indirect_descriptors) {
util_vma_heap_init(&device->vma_desc,
device->physical->va.indirect_descriptor_pool.addr,
device->physical->va.indirect_descriptor_pool.size);
} else {
util_vma_heap_init(&device->vma_desc,
device->physical->va.direct_descriptor_pool.addr,
device->physical->va.direct_descriptor_pool.size);
}
list_inithead(&device->memory_objects);
list_inithead(&device->image_private_objects);
@@ -3363,18 +3370,20 @@ VkResult anv_CreateDevice(
if (result != VK_SUCCESS)
goto fail_bindless_surface_state_pool;
result = anv_state_pool_init(&device->push_descriptor_pool, device,
"push descriptor pool",
device->physical->va.push_descriptor_pool.addr,
0, 4096);
if (result != VK_SUCCESS)
goto fail_binding_table_pool;
if (device->physical->indirect_descriptors) {
result = anv_state_pool_init(&device->indirect_push_descriptor_pool, device,
"indirect push descriptor pool",
device->physical->va.indirect_push_descriptor_pool.addr,
0, 4096);
if (result != VK_SUCCESS)
goto fail_binding_table_pool;
}
if (device->info->has_aux_map) {
device->aux_map_ctx = intel_aux_map_init(device, &aux_map_allocator,
&physical_device->info);
if (!device->aux_map_ctx)
goto fail_push_descriptor_pool;
goto fail_indirect_push_descriptor_pool;
}
result = anv_device_alloc_bo(device, "workaround", 8192,
@@ -3619,8 +3628,9 @@ VkResult anv_CreateDevice(
intel_aux_map_finish(device->aux_map_ctx);
device->aux_map_ctx = NULL;
}
fail_push_descriptor_pool:
anv_state_pool_finish(&device->push_descriptor_pool);
fail_indirect_push_descriptor_pool:
if (device->physical->indirect_descriptors)
anv_state_pool_finish(&device->indirect_push_descriptor_pool);
fail_binding_table_pool:
anv_state_pool_finish(&device->binding_table_pool);
fail_bindless_surface_state_pool:
@@ -3741,7 +3751,8 @@ void anv_DestroyDevice(
device->aux_map_ctx = NULL;
}
anv_state_pool_finish(&device->push_descriptor_pool);
if (device->physical->indirect_descriptors)
anv_state_pool_finish(&device->indirect_push_descriptor_pool);
anv_state_pool_finish(&device->binding_table_pool);
if (device->info->verx10 >= 125)
anv_state_pool_finish(&device->scratch_surface_state_pool);

2
src/intel/vulkan/anv_pipeline_cache.c
View File

@@ -127,7 +127,7 @@ anv_shader_bin_create(struct anv_device *device,
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH,
.value = device->physical->indirect_descriptors ?
(device->physical->va.descriptor_pool.addr >> 32) :
(device->physical->va.indirect_descriptor_pool.addr >> 32) :
(device->physical->va.binding_table_pool.addr >> 32),
};
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {

50
src/intel/vulkan/anv_private.h
View File

@@ -948,17 +948,57 @@ struct anv_physical_device {
} memory;
struct {
/**
* General state pool
*/
struct anv_va_range general_state_pool;
/**
* Low 32bit heap
*/
struct anv_va_range low_heap;
struct anv_va_range dynamic_state_pool;
/**
* Binding table pool
*/
struct anv_va_range binding_table_pool;
/**
* Internal surface states for blorp & push descriptors.
*/
struct anv_va_range internal_surface_state_pool;
/**
* Scratch surfaces (overlaps with internal_surface_state_pool).
*/
struct anv_va_range scratch_surface_state_pool;
/**
* Bindless surface states (used with indirect descriptors)
*/
struct anv_va_range bindless_surface_state_pool;
/**
* Bindless surface & sampler states (used with direct descriptors)
*/
struct anv_va_range direct_descriptor_pool;
/**
* Dynamic state pool
*/
struct anv_va_range dynamic_state_pool;
/**
* Indirect descriptor pool
*/
struct anv_va_range indirect_descriptor_pool;
/**
* Indirect push descriptor pool
*/
struct anv_va_range indirect_push_descriptor_pool;
/**
* Instruction state pool
*/
struct anv_va_range instruction_state_pool;
struct anv_va_range descriptor_pool;
struct anv_va_range push_descriptor_pool;
/**
* Client visible VMA allocation heap
*/
struct anv_va_range client_visible_heap;
/**
* Client heap
*/
struct anv_va_range high_heap;
} va;
@@ -1527,7 +1567,7 @@ struct anv_device {
struct anv_state_pool scratch_surface_state_pool;
struct anv_state_pool internal_surface_state_pool;
struct anv_state_pool bindless_surface_state_pool;
struct anv_state_pool push_descriptor_pool;
struct anv_state_pool indirect_push_descriptor_pool;
struct anv_state_reserved_pool custom_border_colors;
@@ -3545,7 +3585,7 @@ struct anv_cmd_buffer {
struct anv_state_stream surface_state_stream;
struct anv_state_stream dynamic_state_stream;
struct anv_state_stream general_state_stream;
struct anv_state_stream push_descriptor_stream;
struct anv_state_stream indirect_push_descriptor_stream;
VkCommandBufferUsageFlags usage_flags;

28
src/intel/vulkan/anv_va.c
View File

@@ -57,8 +57,9 @@ anv_device_print_vas(struct anv_physical_device *device)
PRINT_HEAP(internal_surface_state_pool);
PRINT_HEAP(scratch_surface_state_pool);
PRINT_HEAP(bindless_surface_state_pool);
PRINT_HEAP(descriptor_pool);
PRINT_HEAP(push_descriptor_pool);
PRINT_HEAP(direct_descriptor_pool);
PRINT_HEAP(indirect_descriptor_pool);
PRINT_HEAP(indirect_push_descriptor_pool);
PRINT_HEAP(instruction_state_pool);
PRINT_HEAP(client_visible_heap);
PRINT_HEAP(high_heap);
@@ -101,8 +102,10 @@ anv_physical_device_init_va_ranges(struct anv_physical_device *device)
_1Gb - address);
address = va_add(&device->va.low_heap, address, _1Gb);
/* The STATE_BASE_ADDRESS can only express up to 4Gb - 4Kb */
address = va_add(&device->va.dynamic_state_pool, address, 4 * _1Gb - 4096);
/* PRMs & simulation disagrees on the actual size of this heap. Take the
* smallest (simulation) so that it works everywhere.
*/
address = va_add(&device->va.dynamic_state_pool, address, _4Gb - 4096);
address = align64(address, _1Gb);
/* The following addresses have to be located in a 4Gb range so that the
@@ -126,16 +129,21 @@ anv_physical_device_init_va_ranges(struct anv_physical_device *device)
* this pool.
*/
address = va_add(&device->va.bindless_surface_state_pool, address, 2 * _1Gb);
/* Descriptor buffers can go anywhere */
address = align64(address, _4Gb);
address = va_add(&device->va.descriptor_pool, address, 3 * _1Gb);
address = va_add(&device->va.push_descriptor_pool, address, _1Gb);
} else {
/* With direct descriptor, descriptors set buffers are allocated
* here.
*/
address = va_add(&device->va.descriptor_pool, address, 2 * _1Gb);
address = va_add(&device->va.direct_descriptor_pool, address, 2 * _1Gb);
}
if (device->indirect_descriptors) {
/* With indirect descriptors, descriptor buffers can go anywhere, they
* just need to be in a 4Gb aligned range, so all shader accesses can
* use a relocatable upper dword for the 64bit address.
*/
address = align64(address, _4Gb);
address = va_add(&device->va.indirect_descriptor_pool, address, 3 * _1Gb);
address = va_add(&device->va.indirect_push_descriptor_pool, address, _1Gb);
}
/* We use a trick to compute constant data offsets in the shaders to avoid

4
src/intel/vulkan/genX_init_state.c
View File

@@ -285,11 +285,11 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
sba.BindlessSurfaceStateSize =
(device->physical->va.binding_table_pool.size +
device->physical->va.internal_surface_state_pool.size +
device->physical->va.descriptor_pool.size) - 1;
device->physical->va.direct_descriptor_pool.size) - 1;
sba.BindlessSamplerStateBufferSize =
(device->physical->va.binding_table_pool.size +
device->physical->va.internal_surface_state_pool.size +
device->physical->va.descriptor_pool.size) / 4096 - 1;
device->physical->va.direct_descriptor_pool.size) / 4096 - 1;
sba.BindlessSurfaceStateMOCS = sba.BindlessSamplerStateMOCS = mocs;
sba.BindlessSurfaceStateBaseAddressModifyEnable =
sba.BindlessSamplerStateBaseAddressModifyEnable = true;

4
src/intel/vulkan/i915/anv_batch_chain.c
View File

@@ -374,8 +374,8 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf,
return result;
}
if (device->physical->va.push_descriptor_pool.size > 0) {
result = pin_state_pool(device, execbuf, &device->push_descriptor_pool);
if (device->physical->va.indirect_push_descriptor_pool.size > 0) {
result = pin_state_pool(device, execbuf, &device->indirect_push_descriptor_pool);
if (result != VK_SUCCESS)
return result;
}