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radv/amdgpu: Remove ctx_query_reset_status

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We don't use this anymore, it is all dead code.

Signed-off-by: Joshua Ashton <joshua@froggi.es>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27091>
This commit is contained in:
Joshua Ashton
2024-01-16 12:31:25 +00:00
committed by Marge Bot
parent f62bdde703
commit ed4ef4dc65
2 changed files with 0 additions and 35 deletions
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8
src/amd/vulkan/radv_radeon_winsys.h
View File

@@ -102,12 +102,6 @@ enum radeon_value_id {
RADEON_CURRENT_MCLK,
};
enum radv_reset_status {
RADV_NO_RESET,
RADV_GUILTY_CONTEXT_RESET,
RADV_INNOCENT_CONTEXT_RESET,
};
struct radeon_cmdbuf {
/* These are uint64_t to tell the compiler that buf can't alias them.
* If they're uint32_t the generated code needs to redundantly
@@ -282,8 +276,6 @@ struct radeon_winsys {
int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
enum radv_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *rwctx);
enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type, bool is_secondary);

27
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View File

@@ -1487,32 +1487,6 @@ radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx, enum amd_ip_type ip_t
return true;
}
static enum radv_reset_status
radv_amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
{
int ret;
struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
uint64_t flags;
ret = amdgpu_cs_query_reset_state2(ctx->ctx, &flags);
if (ret) {
fprintf(stderr, "radv/amdgpu: amdgpu_cs_query_reset_state2 failed. (%i)\n", ret);
return RADV_NO_RESET;
}
if (flags & AMDGPU_CTX_QUERY2_FLAGS_RESET) {
if (flags & AMDGPU_CTX_QUERY2_FLAGS_GUILTY) {
/* Some job from this context once caused a GPU hang */
return RADV_GUILTY_CONTEXT_RESET;
} else {
/* Some job from other context caused a GPU hang */
return RADV_INNOCENT_CONTEXT_RESET;
}
}
return RADV_NO_RESET;
}
static uint32_t
radv_to_amdgpu_pstate(enum radeon_ctx_pstate radv_pstate)
{
@@ -1802,7 +1776,6 @@ radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
ws->base.ctx_set_pstate = radv_amdgpu_ctx_set_pstate;
ws->base.ctx_query_reset_status = radv_amdgpu_ctx_query_reset_status;
ws->base.cs_domain = radv_amdgpu_cs_domain;
ws->base.cs_create = radv_amdgpu_cs_create;
ws->base.cs_destroy = radv_amdgpu_cs_destroy;