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gallium: Drop the unused SFL/STR opcodes.

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Nothing generated them.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
This commit is contained in:
Eric Anholt
2014-11-12 14:36:19 -08:00
parent dc00b382b5
commit ecfe9e2ad2
13 changed files with 10 additions and 150 deletions
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24
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
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@@ -691,28 +691,6 @@ const struct lp_build_tgsi_action scs_action = {
scs_emit /* emit */
};
/* TGSI_OPCODE_SFL */
static void
sfl_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
emit_data->output[emit_data->chan] = bld_base->base.zero;
}
/* TGSI_OPCODE_STR */
static void
str_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
emit_data->output[emit_data->chan] = bld_base->base.one;
}
/* TGSI_OPCODE_SUB */
static void
sub_emit(
@@ -958,8 +936,6 @@ lp_set_default_actions(struct lp_build_tgsi_context * bld_base)
bld_base->op_actions[TGSI_OPCODE_MUL].emit = mul_emit;
bld_base->op_actions[TGSI_OPCODE_DIV].emit = fdiv_emit;
bld_base->op_actions[TGSI_OPCODE_RCP].emit = rcp_emit;
bld_base->op_actions[TGSI_OPCODE_SFL].emit = sfl_emit;
bld_base->op_actions[TGSI_OPCODE_STR].emit = str_emit;
bld_base->op_actions[TGSI_OPCODE_SUB].emit = sub_emit;
bld_base->op_actions[TGSI_OPCODE_UARL].emit = mov_emit;

8
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
View File

@@ -722,10 +722,6 @@ lp_emit_instruction_aos(
dst0 = lp_build_select(&bld->bld_base.base, tmp0, bld->bld_base.base.one, bld->bld_base.base.zero);
break;
case TGSI_OPCODE_SFL:
dst0 = bld->bld_base.base.zero;
break;
case TGSI_OPCODE_SGT:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL);
@@ -753,10 +749,6 @@ lp_emit_instruction_aos(
dst0 = lp_build_select(&bld->bld_base.base, tmp0, bld->bld_base.base.one, bld->bld_base.base.zero);
break;
case TGSI_OPCODE_STR:
dst0 = bld->bld_base.base.one;
break;
case TGSI_OPCODE_TEX:
dst0 = emit_tex(bld, inst, LP_BLD_TEX_MODIFIER_NONE);
break;

47
src/gallium/auxiliary/tgsi/tgsi_exec.c
View File

@@ -451,24 +451,6 @@ micro_sne(union tgsi_exec_channel *dst,
dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
}
static void
micro_sfl(union tgsi_exec_channel *dst)
{
dst->f[0] = 0.0f;
dst->f[1] = 0.0f;
dst->f[2] = 0.0f;
dst->f[3] = 0.0f;
}
static void
micro_str(union tgsi_exec_channel *dst)
{
dst->f[0] = 1.0f;
dst->f[1] = 1.0f;
dst->f[2] = 1.0f;
dst->f[3] = 1.0f;
}
static void
micro_trunc(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
@@ -2446,27 +2428,6 @@ exec_declaration(struct tgsi_exec_machine *mach,
}
}
typedef void (* micro_op)(union tgsi_exec_channel *dst);
static void
exec_vector(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst,
micro_op op,
enum tgsi_exec_datatype dst_datatype)
{
unsigned int chan;
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
union tgsi_exec_channel dst;
op(&dst);
store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
}
}
}
typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src);
@@ -3734,10 +3695,6 @@ exec_instruction(
exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_SFL:
exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_SGT:
exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
@@ -3754,10 +3711,6 @@ exec_instruction(
exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_STR:
exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_TEX:
/* simple texture lookup */
/* src[0] = texcoord */

4
src/gallium/auxiliary/tgsi/tgsi_info.c
View File

@@ -83,12 +83,12 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, "PK4UB", TGSI_OPCODE_PK4UB },
{ 0, 1, 0, 0, 0, 1, NONE, "", 44 }, /* removed */
{ 1, 2, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ },
{ 1, 2, 0, 0, 0, 0, REPL, "SFL", TGSI_OPCODE_SFL },
{ 0, 1, 0, 0, 0, 1, NONE, "", 46 }, /* removed */
{ 1, 2, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT },
{ 1, 1, 0, 0, 0, 0, REPL, "SIN", TGSI_OPCODE_SIN },
{ 1, 2, 0, 0, 0, 0, COMP, "SLE", TGSI_OPCODE_SLE },
{ 1, 2, 0, 0, 0, 0, COMP, "SNE", TGSI_OPCODE_SNE },
{ 1, 2, 0, 0, 0, 0, REPL, "STR", TGSI_OPCODE_STR },
{ 0, 1, 0, 0, 0, 1, NONE, "", 51 }, /* removed */
{ 1, 2, 1, 0, 0, 0, OTHR, "TEX", TGSI_OPCODE_TEX },
{ 1, 4, 1, 0, 0, 0, OTHR, "TXD", TGSI_OPCODE_TXD },
{ 1, 2, 1, 0, 0, 0, OTHR, "TXP", TGSI_OPCODE_TXP },

2
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
View File

@@ -97,12 +97,10 @@ OP11(PK2US)
OP11(PK4B)
OP11(PK4UB)
OP12(SEQ)
OP12(SFL)
OP12(SGT)
OP11(SIN)
OP12(SLE)
OP12(SNE)
OP12(STR)
OP12_TEX(TEX)
OP14_TEX(TXD)
OP12_TEX(TXP)

13
src/gallium/docs/source/tgsi.rst
View File

@@ -489,19 +489,6 @@ while DDY is allowed to be the same for the entire 2x2 quad.
dst.w = (src0.w == src1.w) ? 1.0F : 0.0F
.. opcode:: SFL - Set On False
This instruction replicates its result.
.. math::
dst = 0.0F
.. note::
Considered for removal.
.. opcode:: SGT - Set On Greater Than
.. math::

26
src/gallium/drivers/ilo/shader/toy_tgsi.c
View File

@@ -650,28 +650,6 @@ aos_PK2H(struct toy_compiler *tc,
tc_OR(tc, tdst_ud(dst[0]), h1, tsrc_from(tmp));
}
static void
aos_SFL(struct toy_compiler *tc,
const struct tgsi_full_instruction *tgsi_inst,
struct toy_dst *dst,
struct toy_src *src)
{
assert(!"SFL untested");
tc_MOV(tc, dst[0], tsrc_imm_f(0.0f));
}
static void
aos_STR(struct toy_compiler *tc,
const struct tgsi_full_instruction *tgsi_inst,
struct toy_dst *dst,
struct toy_src *src)
{
assert(!"STR untested");
tc_MOV(tc, dst[0], tsrc_imm_f(1.0f));
}
static void
aos_UP2H(struct toy_compiler *tc,
const struct tgsi_full_instruction *tgsi_inst,
@@ -839,12 +817,10 @@ static const toy_tgsi_translate aos_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_PK4B] = aos_unsupported,
[TGSI_OPCODE_PK4UB] = aos_unsupported,
[TGSI_OPCODE_SEQ] = aos_set_on_cond,
[TGSI_OPCODE_SFL] = aos_SFL,
[TGSI_OPCODE_SGT] = aos_set_on_cond,
[TGSI_OPCODE_SIN] = aos_simple,
[TGSI_OPCODE_SLE] = aos_set_on_cond,
[TGSI_OPCODE_SNE] = aos_set_on_cond,
[TGSI_OPCODE_STR] = aos_STR,
[TGSI_OPCODE_TEX] = aos_tex,
[TGSI_OPCODE_TXD] = aos_tex,
[TGSI_OPCODE_TXP] = aos_tex,
@@ -1386,12 +1362,10 @@ static const toy_tgsi_translate soa_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_PK4B] = soa_unsupported,
[TGSI_OPCODE_PK4UB] = soa_unsupported,
[TGSI_OPCODE_SEQ] = soa_per_channel,
[TGSI_OPCODE_SFL] = soa_per_channel,
[TGSI_OPCODE_SGT] = soa_per_channel,
[TGSI_OPCODE_SIN] = soa_scalar_replicate,
[TGSI_OPCODE_SLE] = soa_per_channel,
[TGSI_OPCODE_SNE] = soa_per_channel,
[TGSI_OPCODE_STR] = soa_per_channel,
[TGSI_OPCODE_TEX] = soa_passthrough,
[TGSI_OPCODE_TXD] = soa_passthrough,
[TGSI_OPCODE_TXP] = soa_passthrough,

6
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
View File

@@ -492,9 +492,6 @@ nv50_ir::CondCode Instruction::getSetCond() const
return CC_NEU;
case TGSI_OPCODE_USNE:
return CC_NE;
case TGSI_OPCODE_SFL:
return CC_NEVER;
case TGSI_OPCODE_STR:
default:
return CC_ALWAYS;
}
@@ -537,7 +534,6 @@ static nv50_ir::operation translateOpcode(uint opcode)
NV50_IR_OPCODE_CASE(KILL, DISCARD);
NV50_IR_OPCODE_CASE(SEQ, SET);
NV50_IR_OPCODE_CASE(SFL, SET);
NV50_IR_OPCODE_CASE(SGT, SET);
NV50_IR_OPCODE_CASE(SIN, SIN);
NV50_IR_OPCODE_CASE(SLE, SET);
@@ -2533,11 +2529,9 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_SGE:
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_SFL:
case TGSI_OPCODE_SGT:
case TGSI_OPCODE_SLE:
case TGSI_OPCODE_SNE:
case TGSI_OPCODE_STR:
case TGSI_OPCODE_FSEQ:
case TGSI_OPCODE_FSGE:
case TGSI_OPCODE_FSLT:

6
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
View File

@@ -715,9 +715,6 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc,
case TGSI_OPCODE_SEQ:
nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_SFL:
nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_SGE:
nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
break;
@@ -755,9 +752,6 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc,
}
break;
}
case TGSI_OPCODE_STR:
nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_SUB:
nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
break;

6
src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
View File

@@ -655,9 +655,6 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc,
case TGSI_OPCODE_SEQ:
nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_SFL:
nvfx_vp_emit(vpc, arith(sat, VEC, SFL, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_SGE:
nvfx_vp_emit(vpc, arith(sat, VEC, SGE, dst, mask, src[0], src[1], none));
break;
@@ -679,9 +676,6 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc,
case TGSI_OPCODE_SSG:
nvfx_vp_emit(vpc, arith(sat, VEC, SSG, dst, mask, src[0], none, none));
break;
case TGSI_OPCODE_STR:
nvfx_vp_emit(vpc, arith(sat, VEC, STR, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_SUB:
nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, neg(src[1])));
break;

2
src/gallium/drivers/r300/r300_tgsi_to_rc.c
View File

@@ -72,12 +72,10 @@ static unsigned translate_opcode(unsigned opcode)
/* case TGSI_OPCODE_PK4B: return RC_OPCODE_PK4B; */
/* case TGSI_OPCODE_PK4UB: return RC_OPCODE_PK4UB; */
case TGSI_OPCODE_SEQ: return RC_OPCODE_SEQ;
case TGSI_OPCODE_SFL: return RC_OPCODE_SFL;
case TGSI_OPCODE_SGT: return RC_OPCODE_SGT;
case TGSI_OPCODE_SIN: return RC_OPCODE_SIN;
case TGSI_OPCODE_SLE: return RC_OPCODE_SLE;
case TGSI_OPCODE_SNE: return RC_OPCODE_SNE;
/* case TGSI_OPCODE_STR: return RC_OPCODE_STR; */
case TGSI_OPCODE_TEX: return RC_OPCODE_TEX;
case TGSI_OPCODE_TXD: return RC_OPCODE_TXD;
case TGSI_OPCODE_TXP: return RC_OPCODE_TXP;

12
src/gallium/drivers/r600/r600_shader.c
View File

@@ -7234,12 +7234,12 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
{TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{44, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
{TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{46, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
{TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
{TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
{TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
{TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
{51, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
{TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
{TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
@@ -7433,12 +7433,12 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{44, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
{TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{46, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
{TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
{TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
{TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
{TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
{51, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
{TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
{TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
@@ -7632,12 +7632,12 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
{TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{44, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
{TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{46, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
{TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
{TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
{TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
{TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
{51, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
{TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
{TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},

4
src/gallium/include/pipe/p_shader_tokens.h
View File

@@ -329,12 +329,12 @@ struct tgsi_property_data {
#define TGSI_OPCODE_PK4UB 43
/* gap */
#define TGSI_OPCODE_SEQ 45
#define TGSI_OPCODE_SFL 46
/* gap */
#define TGSI_OPCODE_SGT 47
#define TGSI_OPCODE_SIN 48
#define TGSI_OPCODE_SLE 49
#define TGSI_OPCODE_SNE 50
#define TGSI_OPCODE_STR 51
/* gap */
#define TGSI_OPCODE_TEX 52
#define TGSI_OPCODE_TXD 53
#define TGSI_OPCODE_TXP 54