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intel/blorp: move Wa_18019816803 out of blorp code

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The driver already need to track this WA for blorp. We can completely
remove any blorp code dealing with this and instead have the flush
required by the workaround be combined with potential other flushes
the driver already has to insert before blorp operations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
This commit is contained in:
Lionel Landwerlin
2023-11-08 12:14:09 +02:00
committed by Marge Bot
parent 6e85fa8a80
commit ec3f8c0d42
4 changed files with 20 additions and 21 deletions
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15
src/gallium/drivers/iris/iris_blorp.c
View File

@@ -287,6 +287,7 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch,
{
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
struct iris_batch *batch = blorp_batch->driver_batch;
uint32_t pc_flags = 0;
#if GFX_VER >= 11
/* The PIPE_CONTROL command description says:
@@ -297,10 +298,8 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch,
* is set due to new association of BTI, PS Scoreboard Stall bit must
* be set in this packet."
*/
iris_emit_pipe_control_flush(batch,
"workaround: RT BTI change [blorp]",
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
pc_flags = PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_STALL_AT_SCOREBOARD;
#endif
/* Check if blorp ds state matches ours. */
@@ -308,11 +307,17 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch,
const bool blorp_ds_state =
params->depth.enabled || params->stencil.enabled;
if (ice->state.ds_write_state != blorp_ds_state) {
blorp_batch->flags |= BLORP_BATCH_NEED_PSS_STALL_SYNC;
pc_flags |= PIPE_CONTROL_PSS_STALL_SYNC;
ice->state.ds_write_state = blorp_ds_state;
}
}
if (pc_flags != 0) {
iris_emit_pipe_control_flush(batch,
"workaround: prior to [blorp]",
pc_flags);
}
if (params->depth.enabled &&
!(blorp_batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
genX(emit_depth_state_workarounds)(ice, batch, &params->depth.surf);

3
src/intel/blorp/blorp.h
View File

@@ -111,9 +111,6 @@ enum blorp_batch_flags {
/** Use the hardware blitter to perform any operations in this batch */
BLORP_BATCH_USE_BLITTER = (1 << 4),
/** Need a PSS Stall Sync, Wa_18019816803. */
BLORP_BATCH_NEED_PSS_STALL_SYNC = (1 << 5),
};
struct blorp_batch {

12
src/intel/blorp/blorp_genX_exec.h
View File

@@ -1259,18 +1259,6 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
return 0;
GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &ds);
#if GFX_VERx10 >= 125
/* Check if need PSS Stall sync. */
if (intel_needs_workaround(batch->blorp->compiler->devinfo, 18019816803) &&
batch->flags & BLORP_BATCH_NEED_PSS_STALL_SYNC) {
blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.PSSStallSyncEnable = true;
}
batch->flags &= ~BLORP_BATCH_NEED_PSS_STALL_SYNC;
}
#endif
#else
uint32_t offset;
void *state = blorp_alloc_dynamic_state(batch,

11
src/intel/vulkan/genX_blorp_exec.c
View File

@@ -309,9 +309,18 @@ blorp_exec_on_render(struct blorp_batch *batch,
if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
bool blorp_ds_state = params->depth.enabled || params->stencil.enabled;
if (cmd_buffer->state.gfx.ds_write_state != blorp_ds_state) {
batch->flags |= BLORP_BATCH_NEED_PSS_STALL_SYNC;
/* Flag the change in ds_write_state so that the next pipeline use
* will trigger a PIPE_CONTROL too.
*/
cmd_buffer->state.gfx.ds_write_state = blorp_ds_state;
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WA_18019816803);
/* Add the stall that will flush prior to the blorp operation by
* genX(cmd_buffer_apply_pipe_flushes)
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_PSS_STALL_SYNC_BIT,
"Wa_18019816803");
}
}
#endif