anv/pipeline: Set StencilBufferWriteEnable from the pipeline
The hardware docs say that StencilBufferWriteEnable should only be set if StencilTestEnable is set. It seems reasonable to set them together.
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@@ -581,9 +581,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
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.StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
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d->stencil_write_mask.back != 0,
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.StencilTestMask = d->stencil_compare_mask.front & 0xff,
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.StencilWriteMask = d->stencil_write_mask.front & 0xff,
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@@ -95,6 +95,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
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.DoubleSidedStencilEnable = true,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilBufferWriteEnable = info->stencilTestEnable,
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.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
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@@ -384,9 +384,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
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GENX(3DSTATE_WM_DEPTH_STENCIL_header),
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.StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
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d->stencil_write_mask.back != 0,
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.StencilTestMask = d->stencil_compare_mask.front & 0xff,
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.StencilWriteMask = d->stencil_write_mask.front & 0xff,
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@@ -227,6 +227,7 @@ emit_ds_state(struct anv_pipeline *pipeline,
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.DoubleSidedStencilEnable = true,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilBufferWriteEnable = info->stencilTestEnable,
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.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
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