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anv/pipeline: Set StencilBufferWriteEnable from the pipeline

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The hardware docs say that StencilBufferWriteEnable should only be set if
StencilTestEnable is set.  It seems reasonable to set them together.
This commit is contained in:
Jason Ekstrand
2016-03-04 10:45:24 -08:00
parent fcd8e57185
commit ec18fef88d
4 changed files with 2 additions and 6 deletions
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src/intel/vulkan/gen7_pipeline.c
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@@ -95,6 +95,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
.DoubleSidedStencilEnable = true,
.StencilTestEnable = info->stencilTestEnable,
.StencilBufferWriteEnable = info->stencilTestEnable,
.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],