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intel/compiler: Store start of ICP handles in TCS thread payload struct

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Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
This commit is contained in:
Caio Oliveira
2022-08-19 17:31:37 -07:00
committed by Marge Bot
parent 2622fc3af1
commit eb837dd23b
3 changed files with 14 additions and 12 deletions
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1
src/intel/compiler/brw_fs.h
View File

@@ -98,6 +98,7 @@ struct tcs_thread_payload : public thread_payload {
fs_reg patch_urb_output; fs_reg patch_urb_output;
fs_reg primitive_id; fs_reg primitive_id;
fs_reg icp_handle_start;
}; };
struct fs_thread_payload : public thread_payload { struct fs_thread_payload : public thread_payload {

7
src/intel/compiler/brw_fs_nir.cpp
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@@ -2714,8 +2714,7 @@ fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder &bld,
const nir_src &vertex_src = instr->src[0]; const nir_src &vertex_src = instr->src[0];
nir_intrinsic_instr *vertex_intrin = nir_src_as_intrinsic(vertex_src); nir_intrinsic_instr *vertex_intrin = nir_src_as_intrinsic(vertex_src);
/* ICP Handles start in r1. */ const fs_reg start = tcs_payload().icp_handle_start;
fs_reg start = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
fs_reg icp_handle; fs_reg icp_handle;
@@ -2757,11 +2756,9 @@ fs_visitor::get_tcs_multi_patch_icp_handle(const fs_builder &bld,
nir_intrinsic_instr *instr) nir_intrinsic_instr *instr)
{ {
struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key; struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
const nir_src &vertex_src = instr->src[0]; const nir_src &vertex_src = instr->src[0];
fs_reg start = retype(brw_vec8_grf(tcs_prog_data->include_primitive_id ? 3 : 2, 0), const fs_reg start = tcs_payload().icp_handle_start;
BRW_REGISTER_TYPE_UD);
if (nir_src_is_const(vertex_src)) if (nir_src_is_const(vertex_src))
return byte_offset(start, nir_src_as_uint(vertex_src) * REG_SIZE); return byte_offset(start, nir_src_as_uint(vertex_src) * REG_SIZE);

18
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -36,6 +36,8 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
primitive_id = brw_vec1_grf(0, 1); primitive_id = brw_vec1_grf(0, 1);
/* r1-r4 contain the ICP handles. */ /* r1-r4 contain the ICP handles. */
icp_handle_start = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
num_regs = 5; num_regs = 5;
} else { } else {
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH); assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
@@ -43,14 +45,16 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
patch_urb_output = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD); patch_urb_output = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
if (tcs_prog_data->include_primitive_id) unsigned r = 2;
primitive_id = brw_vec8_grf(2, 0);
/* r1 contains output handles, r2 may contain primitive ID, then the if (tcs_prog_data->include_primitive_id)
* ICP handles occupy the next 1-32 registers. primitive_id = brw_vec8_grf(r++, 0);
*/
num_regs = 2 + tcs_prog_data->include_primitive_id + /* ICP handles occupy the next 1-32 registers. */
tcs_key->input_vertices; icp_handle_start = retype(brw_vec8_grf(r, 0), BRW_REGISTER_TYPE_UD);
r += tcs_key->input_vertices;
num_regs = r;
} }
} }