diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 6e017a449c1..8947bbe5dd2 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -98,6 +98,7 @@ struct tcs_thread_payload : public thread_payload {
 
    fs_reg patch_urb_output;
    fs_reg primitive_id;
+   fs_reg icp_handle_start;
 };
 
 struct fs_thread_payload : public thread_payload {
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index d1cfb68123f..fb12ceb825c 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2714,8 +2714,7 @@ fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder &bld,
    const nir_src &vertex_src = instr->src[0];
    nir_intrinsic_instr *vertex_intrin = nir_src_as_intrinsic(vertex_src);
 
-   /* ICP Handles start in r1. */
-   fs_reg start = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
+   const fs_reg start = tcs_payload().icp_handle_start;
 
    fs_reg icp_handle;
 
@@ -2757,11 +2756,9 @@ fs_visitor::get_tcs_multi_patch_icp_handle(const fs_builder &bld,
                                            nir_intrinsic_instr *instr)
 {
    struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
-   struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
    const nir_src &vertex_src = instr->src[0];
 
-   fs_reg start = retype(brw_vec8_grf(tcs_prog_data->include_primitive_id ? 3 : 2, 0),
-                         BRW_REGISTER_TYPE_UD);
+   const fs_reg start = tcs_payload().icp_handle_start;
 
    if (nir_src_is_const(vertex_src))
       return byte_offset(start, nir_src_as_uint(vertex_src) * REG_SIZE);
diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index 490efdea007..aa5435ff094 100644
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -36,6 +36,8 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
       primitive_id = brw_vec1_grf(0, 1);
 
       /* r1-r4 contain the ICP handles. */
+      icp_handle_start = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
+
       num_regs = 5;
    } else {
       assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
@@ -43,14 +45,16 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
 
       patch_urb_output = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
 
-      if (tcs_prog_data->include_primitive_id)
-         primitive_id = brw_vec8_grf(2, 0);
+      unsigned r = 2;
 
-      /* r1 contains output handles, r2 may contain primitive ID, then the
-       * ICP handles occupy the next 1-32 registers.
-       */
-      num_regs = 2 + tcs_prog_data->include_primitive_id +
-                 tcs_key->input_vertices;
+      if (tcs_prog_data->include_primitive_id)
+         primitive_id = brw_vec8_grf(r++, 0);
+
+      /* ICP handles occupy the next 1-32 registers. */
+      icp_handle_start = retype(brw_vec8_grf(r, 0), BRW_REGISTER_TYPE_UD);
+      r += tcs_key->input_vertices;
+
+      num_regs = r;
    }
 }