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radv,aco: fix use of texop_samples_identical in the resolve meta path

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The return value of this texture intrinsic should be a NIR 1-bit bool.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7236>
This commit is contained in:
Samuel Pitoiset
2020-10-20 16:56:29 +02:00
parent eacdad7ea0
commit eb6877d3af
3 changed files with 10 additions and 15 deletions
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7
src/amd/compiler/aco_instruction_selection.cpp
View File

@@ -9049,13 +9049,10 @@ void visit_tex(isel_context *ctx, nir_tex_instr *instr)
ctx->block->instructions.emplace_back(std::move(tex));
if (instr->op == nir_texop_samples_identical) {
assert(dmask == 1 && dst.regClass() == v1);
assert(dmask == 1 && dst.regClass() == bld.lm);
assert(dst.id() != tmp_dst.id());
Temp tmp = bld.tmp(bld.lm);
bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(dst), Operand(0u), tmp_dst).def(0).setHint(vcc);
} else {
expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
}

12
src/amd/compiler/aco_instruction_selection_setup.cpp
View File

@@ -918,17 +918,15 @@ void init_context(isel_context *ctx, nir_shader *shader)
}
case nir_instr_type_tex: {
nir_tex_instr* tex = nir_instr_as_tex(instr);
unsigned size = tex->dest.ssa.num_components;
RegType type = nir_dest_is_divergent(tex->dest) ? RegType::vgpr : RegType::sgpr;
if (tex->dest.ssa.bit_size == 64)
size *= 2;
if (tex->op == nir_texop_texture_samples) {
assert(!tex->dest.ssa.divergent);
}
if (nir_dest_is_divergent(tex->dest))
allocated[tex->dest.ssa.index] = Temp(0, RegClass(RegType::vgpr, size));
else
allocated[tex->dest.ssa.index] = Temp(0, RegClass(RegType::sgpr, size));
RegClass rc = get_reg_class(ctx, type, tex->dest.ssa.num_components,
tex->dest.ssa.bit_size);
allocated[tex->dest.ssa.index] = Temp(0, rc);
break;
}
case nir_instr_type_parallel_copy: {

6
src/amd/vulkan/radv_meta.c
View File

@@ -614,14 +614,14 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
tex_all_same->src[0].src = nir_src_for_ssa(img_coord);
tex_all_same->src[1].src_type = nir_tex_src_texture_deref;
tex_all_same->src[1].src = nir_src_for_ssa(input_img_deref);
tex_all_same->dest_type = nir_type_float;
tex_all_same->dest_type = nir_type_uint;
tex_all_same->is_array = false;
tex_all_same->coord_components = 2;
nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 32, "tex");
nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 1, "tex");
nir_builder_instr_insert(b, &tex_all_same->instr);
nir_ssa_def *all_same = nir_ieq(b, &tex_all_same->dest.ssa, nir_imm_int(b, 0));
nir_ssa_def *all_same = nir_ieq(b, &tex_all_same->dest.ssa, nir_imm_bool(b, false));
nir_push_if(b, all_same);
for (int i = 1; i < samples; i++) {
nir_tex_instr *tex_add = nir_tex_instr_create(b->shader, 3);