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freedreno,tu: Move varying interp and varying repl modes to xml

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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
This commit is contained in:
Danylo Piliaiev
2024-01-18 14:23:53 +01:00
committed by Marge Bot
parent 78c843230c
commit eb1e71e707
3 changed files with 16 additions and 22 deletions
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16
src/freedreno/registers/adreno/a6xx.xml
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@@ -3044,11 +3044,27 @@ to upconvert to 32b float internally?
<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> <reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/>
<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/> <reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/>
<enum name="a6xx_varying_interp_mode">
<value value="0" name="INTERP_SMOOTH"/>
<value value="1" name="INTERP_FLAT"/>
<value value="2" name="INTERP_ZERO"/>
<value value="3" name="INTERP_ONE"/>
</enum>
<enum name="a6xx_varying_ps_repl_mode">
<value value="0" name="PS_REPL_NONE"/>
<value value="1" name="PS_REPL_S"/>
<value value="2" name="PS_REPL_T"/>
<value value="3" name="PS_REPL_ONE_MINUS_T"/>
</enum>
<!-- 0x9109-0x91ff invalid --> <!-- 0x9109-0x91ff invalid -->
<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit"> <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit">
<doc>Packed array of a6xx_varying_interp_mode</doc>
<reg32 offset="0x0" name="MODE"/> <reg32 offset="0x0" name="MODE"/>
</array> </array>
<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit"> <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit">
<doc>Packed array of a6xx_varying_ps_repl_mode</doc>
<reg32 offset="0x0" name="MODE"/> <reg32 offset="0x0" name="MODE"/>
</array> </array>

15
src/freedreno/vulkan/tu_pipeline.cc
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@@ -696,21 +696,6 @@ tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
uint8_t *interp_mode, uint8_t *interp_mode,
uint8_t *ps_repl_mode) uint8_t *ps_repl_mode)
{ {
enum
{
INTERP_SMOOTH = 0,
INTERP_FLAT = 1,
INTERP_ZERO = 2,
INTERP_ONE = 3,
};
enum
{
PS_REPL_NONE = 0,
PS_REPL_S = 1,
PS_REPL_T = 2,
PS_REPL_ONE_MINUS_T = 3,
};
const uint32_t compmask = fs->inputs[index].compmask; const uint32_t compmask = fs->inputs[index].compmask;
/* NOTE: varyings are packed, so if compmask is 0xb then first, second, and /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and

7
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
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@@ -1199,13 +1199,6 @@ emit_interp_state(struct fd_ringbuffer *ring, const struct fd6_program_state *st
bool rasterflat, bool sprite_coord_mode, bool rasterflat, bool sprite_coord_mode,
uint32_t sprite_coord_enable) uint32_t sprite_coord_enable)
{ {
enum {
INTERP_SMOOTH = 0,
INTERP_FLAT = 1,
INTERP_ZERO = 2,
INTERP_ONE = 3,
};
const struct ir3_shader_variant *fs = state->fs; const struct ir3_shader_variant *fs = state->fs;
uint32_t vinterp[8], vpsrepl[8]; uint32_t vinterp[8], vpsrepl[8];