intel/compiler: fix intel_swsb_decode for newer platforms

In the previous patch we adjusted the scoreboard pass to take into
consideration a new case of unordered operations for TGL. Fix the
decoding as well.

v2: use intel_device_info_is_mtl()  (Curro, Jordan)
v3: the part where we export num_sources_from_inst() is now a separate patch
    (Curro).
v4: Work around false positive maybe-unitialized warning since Marge
    uses -Werror=maybe-uninitialized (Marge).

Reviewed-by: Francisco Jerez <currojerez@riseup.net> (v3)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20072>

src/intel/compiler/brw_disasm.c

@@ -1792,13 +1792,44 @@ qtr_ctrl(FILE *file, const struct intel_device_info *devinfo,
    return 0;
 }
 
+static bool
+inst_has_type(const struct brw_isa_info *isa,
+              const brw_inst *inst,
+              enum brw_reg_type type)
+{
+   const struct intel_device_info *devinfo = isa->devinfo;
+   const unsigned num_sources = brw_num_sources_from_inst(isa, inst);
+
+   if (brw_inst_dst_type(devinfo, inst) == type)
+      return true;
+
+   if (num_sources >= 3) {
+      if (brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1)
+         return brw_inst_3src_a1_src0_type(devinfo, inst) == type ||
+                brw_inst_3src_a1_src1_type(devinfo, inst) == type ||
+                brw_inst_3src_a1_src2_type(devinfo, inst) == type;
+      else
+         return brw_inst_3src_a16_src_type(devinfo, inst) == type;
+   } else if (num_sources == 2) {
+      return brw_inst_src0_type(devinfo, inst) == type ||
+             brw_inst_src1_type(devinfo, inst) == type;
+   } else {
+      return brw_inst_src0_type(devinfo, inst) == type;
+   }
+}
+
 static int
 swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
 {
    const struct intel_device_info *devinfo = isa->devinfo;
    const enum opcode opcode = brw_inst_opcode(isa, inst);
    const uint8_t x = brw_inst_swsb(devinfo, inst);
-   const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, opcode, x);
+   const bool is_unordered =
+      opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC ||
+      opcode == BRW_OPCODE_MATH ||
+      (intel_device_info_is_mtl(devinfo) &&
+       inst_has_type(isa, inst, BRW_REGISTER_TYPE_DF));
+   const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, is_unordered, x);
    if (swsb.regdist)
       format(file, " %s@%d",
              (swsb.pipe == TGL_PIPE_FLOAT ? "F" :

src/intel/compiler/brw_eu_defines.h

@@ -1236,15 +1236,13 @@ tgl_swsb_encode(const struct intel_device_info *devinfo, struct tgl_swsb swsb)
  * tgl_swsb.
  */
 static inline struct tgl_swsb
-tgl_swsb_decode(const struct intel_device_info *devinfo, const enum opcode opcode,
+tgl_swsb_decode(const struct intel_device_info *devinfo,
-                const uint8_t x)
+                const bool is_unordered, const uint8_t x)
 {
    if (x & 0x80) {
       const struct tgl_swsb swsb = { (x & 0x70u) >> 4, TGL_PIPE_NONE,
                                      x & 0xfu,
-                                     (opcode == BRW_OPCODE_SEND ||
+                                     is_unordered ?
-                                      opcode == BRW_OPCODE_SENDC ||
-                                      opcode == BRW_OPCODE_MATH) ?
                                      TGL_SBID_SET : TGL_SBID_DST };
       return swsb;
    } else if ((x & 0x70) == 0x20) {