ac/surface: move determing ADDR_FMT_* into a helper function
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23216>
This commit is contained in:
@@ -634,6 +634,47 @@ static int surf_config_sanity(const struct ac_surf_config *config, unsigned flag
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return 0;
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return 0;
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}
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}
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static unsigned bpe_to_format(struct radeon_surf *surf)
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{
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/* The format must be set correctly for the allocation of compressed
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* textures to work. In other cases, setting the bpp is sufficient.
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*/
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if (surf->blk_w == 4 && surf->blk_h == 4) {
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switch (surf->bpe) {
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case 8:
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return ADDR_FMT_BC1;
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case 16:
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return ADDR_FMT_BC3;
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default:
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unreachable("invalid compressed bpe");
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}
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} else {
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switch (surf->bpe) {
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case 1:
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assert(!(surf->flags & RADEON_SURF_ZBUFFER));
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return ADDR_FMT_8;
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case 2:
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assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
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return ADDR_FMT_16;
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case 4:
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assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
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return ADDR_FMT_32;
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case 8:
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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return ADDR_FMT_32_32;
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case 12:
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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return ADDR_FMT_32_32_32;
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case 16:
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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return ADDR_FMT_32_32_32_32;
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default:
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unreachable("invalid bpe");
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}
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}
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return ADDR_FMT_INVALID;
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}
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/* The addrlib pitch alignment is forced to this number for all chips to support interop
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/* The addrlib pitch alignment is forced to this number for all chips to support interop
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* between any 2 chips.
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* between any 2 chips.
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*/
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*/
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@@ -1082,23 +1123,9 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
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assert(0);
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assert(0);
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}
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}
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/* The format must be set correctly for the allocation of compressed
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AddrSurfInfoIn.format = bpe_to_format(surf);
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* textures to work. In other cases, setting the bpp is sufficient.
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if (!compressed)
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*/
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if (compressed) {
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switch (surf->bpe) {
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case 8:
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AddrSurfInfoIn.format = ADDR_FMT_BC1;
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break;
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case 16:
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AddrSurfInfoIn.format = ADDR_FMT_BC3;
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break;
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default:
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assert(0);
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}
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} else {
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AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
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AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
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}
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AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
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AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
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AddrSurfInfoIn.tileIndex = -1;
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AddrSurfInfoIn.tileIndex = -1;
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@@ -1278,6 +1305,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
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if (surf->flags & RADEON_SURF_SBUFFER) {
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if (surf->flags & RADEON_SURF_SBUFFER) {
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AddrSurfInfoIn.tileIndex = stencil_tile_idx;
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AddrSurfInfoIn.tileIndex = stencil_tile_idx;
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AddrSurfInfoIn.bpp = 8;
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AddrSurfInfoIn.bpp = 8;
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AddrSurfInfoIn.format = ADDR_FMT_8;
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AddrSurfInfoIn.flags.depth = 0;
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AddrSurfInfoIn.flags.depth = 0;
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AddrSurfInfoIn.flags.stencil = 1;
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AddrSurfInfoIn.flags.stencil = 1;
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AddrSurfInfoIn.flags.tcCompatible = 0;
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AddrSurfInfoIn.flags.tcCompatible = 0;
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@@ -2168,50 +2196,9 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
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compressed = surf->blk_w == 4 && surf->blk_h == 4;
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compressed = surf->blk_w == 4 && surf->blk_h == 4;
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/* The format must be set correctly for the allocation of compressed
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AddrSurfInfoIn.format = bpe_to_format(surf);
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* textures to work. In other cases, setting the bpp is sufficient. */
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if (!compressed)
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if (compressed) {
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switch (surf->bpe) {
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case 8:
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AddrSurfInfoIn.format = ADDR_FMT_BC1;
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break;
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case 16:
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AddrSurfInfoIn.format = ADDR_FMT_BC3;
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break;
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default:
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assert(0);
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}
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} else {
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switch (surf->bpe) {
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case 1:
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assert(!(surf->flags & RADEON_SURF_ZBUFFER));
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AddrSurfInfoIn.format = ADDR_FMT_8;
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break;
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case 2:
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assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
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AddrSurfInfoIn.format = ADDR_FMT_16;
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break;
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case 4:
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assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
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AddrSurfInfoIn.format = ADDR_FMT_32;
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break;
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case 8:
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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AddrSurfInfoIn.format = ADDR_FMT_32_32;
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break;
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case 12:
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
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break;
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case 16:
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
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break;
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default:
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assert(0);
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}
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AddrSurfInfoIn.bpp = surf->bpe * 8;
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AddrSurfInfoIn.bpp = surf->bpe * 8;
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}
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bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
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bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
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AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
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AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
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