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freedreno: Move UBWC layout into a slices array like the non-UBWC slices.

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This is a little refactor in preparation for UBWC mipmapping support.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Eric Anholt
2019-11-25 11:23:03 -08:00
parent bbe84c6c31
commit ea7631a9a6
6 changed files with 13 additions and 13 deletions
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6
src/freedreno/fdl/freedreno_layout.h
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@@ -81,6 +81,7 @@ struct fdl_slice {
*/ */
struct fdl_layout { struct fdl_layout {
struct fdl_slice slices[MAX_MIP_LEVELS]; struct fdl_slice slices[MAX_MIP_LEVELS];
struct fdl_slice ubwc_slices[MAX_MIP_LEVELS];
uint32_t layer_size; uint32_t layer_size;
bool layer_first : 1; /* see above description */ bool layer_first : 1; /* see above description */
@@ -99,9 +100,6 @@ struct fdl_layout {
uint32_t width0, height0, depth0; uint32_t width0, height0, depth0;
/* UBWC specific fields: */
uint32_t ubwc_offset; /* offset to UBWC meta data */
uint32_t ubwc_pitch;
uint32_t ubwc_size; uint32_t ubwc_size;
}; };
@@ -131,7 +129,7 @@ fdl_ubwc_offset(const struct fdl_layout *layout, unsigned level, unsigned layer)
debug_assert(level == 0); debug_assert(level == 0);
debug_assert(layer == 0); debug_assert(layer == 0);
} }
return layout->ubwc_offset; return layout->ubwc_slices[0].offset;
} }
static inline bool static inline bool

2
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
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@@ -61,7 +61,7 @@ fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
if (fd_resource_ubwc_enabled(rsc, level)) { if (fd_resource_ubwc_enabled(rsc, level)) {
OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0); OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
OUT_RING(ring, OUT_RING(ring,
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_pitch) | A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size)); A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
} else { } else {
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */ OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */

6
src/gallium/drivers/freedreno/a6xx/fd6_image.c
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@@ -196,9 +196,10 @@ static void emit_image_tex(struct fd_ringbuffer *ring, struct fd6_image *img)
OUT_RING(ring, 0x00000000); /* texconst6 */ OUT_RING(ring, 0x00000000); /* texconst6 */
if (ubwc_enabled) { if (ubwc_enabled) {
struct fdl_slice *ubwc_slice = &rsc->layout.ubwc_slices[img->level];
OUT_RELOC(ring, rsc->bo, img->ubwc_offset, 0, 0); OUT_RELOC(ring, rsc->bo, img->ubwc_offset, 0, 0);
OUT_RING(ring, A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size)); OUT_RING(ring, A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size));
OUT_RING(ring, A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_pitch)); OUT_RING(ring, A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_slice->pitch));
} else { } else {
OUT_RING(ring, 0x00000000); /* texconst7 */ OUT_RING(ring, 0x00000000); /* texconst7 */
OUT_RING(ring, 0x00000000); /* texconst8 */ OUT_RING(ring, 0x00000000); /* texconst8 */
@@ -254,9 +255,10 @@ static void emit_image_ssbo(struct fd_ringbuffer *ring, struct fd6_image *img)
OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000);
if (ubwc_enabled) { if (ubwc_enabled) {
struct fdl_slice *ubwc_slice = &rsc->layout.ubwc_slices[img->level];
OUT_RELOCW(ring, rsc->bo, img->ubwc_offset, 0, 0); OUT_RELOCW(ring, rsc->bo, img->ubwc_offset, 0, 0);
OUT_RING(ring, A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size)); OUT_RING(ring, A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size));
OUT_RING(ring, A6XX_IBO_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_pitch)); OUT_RING(ring, A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_slice->pitch));
} else { } else {
OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000);

4
src/gallium/drivers/freedreno/a6xx/fd6_resource.c
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@@ -267,8 +267,8 @@ fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc)
slice->offset += meta_size; slice->offset += meta_size;
} }
rsc->layout.ubwc_offset = 0; rsc->layout.ubwc_slices[0].offset = 0;
rsc->layout.ubwc_pitch = meta_stride; rsc->layout.ubwc_slices[0].pitch = meta_stride;
rsc->layout.ubwc_size = meta_size >> 2; /* in dwords??? */ rsc->layout.ubwc_size = meta_size >> 2; /* in dwords??? */
rsc->layout.tile_mode = TILE6_3; rsc->layout.tile_mode = TILE6_3;

2
src/gallium/drivers/freedreno/a6xx/fd6_texture.c
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@@ -279,7 +279,7 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
if (so->ubwc_enabled) { if (so->ubwc_enabled) {
so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size); so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size);
so->texconst10 |= A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_pitch); so->texconst10 |= A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_slices[lvl].pitch);
} }
so->texconst2 |= A6XX_TEX_CONST_2_TYPE(fd6_tex_type(cso->target)); so->texconst2 |= A6XX_TEX_CONST_2_TYPE(fd6_tex_type(cso->target));

6
src/gallium/drivers/freedreno/freedreno_resource.c
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@@ -223,10 +223,10 @@ fd_try_shadow_resource(struct fd_context *ctx, struct fd_resource *rsc,
/* TODO valid_buffer_range?? */ /* TODO valid_buffer_range?? */
swap(rsc->bo, shadow->bo); swap(rsc->bo, shadow->bo);
swap(rsc->write_batch, shadow->write_batch); swap(rsc->write_batch, shadow->write_batch);
for (int level = 0; level <= prsc->last_level; level++) for (int level = 0; level <= prsc->last_level; level++) {
swap(rsc->layout.slices[level], shadow->layout.slices[level]); swap(rsc->layout.slices[level], shadow->layout.slices[level]);
swap(rsc->layout.ubwc_offset, shadow->layout.ubwc_offset); swap(rsc->layout.ubwc_slices[level], shadow->layout.ubwc_slices[level]);
swap(rsc->layout.ubwc_pitch, shadow->layout.ubwc_pitch); }
swap(rsc->layout.ubwc_size, shadow->layout.ubwc_size); swap(rsc->layout.ubwc_size, shadow->layout.ubwc_size);
rsc->seqno = p_atomic_inc_return(&ctx->screen->rsc_seqno); rsc->seqno = p_atomic_inc_return(&ctx->screen->rsc_seqno);