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radv: gfx11 register changes.

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16419>
This commit is contained in:
Bas Nieuwenhuizen
2022-05-05 13:21:16 +02:00
committed by Marge Bot
parent 9c391fe47e
commit e96a35e6db
6 changed files with 117 additions and 49 deletions
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13
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1161,9 +1161,13 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.attachments) {
struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
format = G_028C70_FORMAT_GFX6(cb->cb_color_info);
format = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11
? G_028C70_FORMAT_GFX11(cb->cb_color_info)
: G_028C70_FORMAT_GFX6(cb->cb_color_info);
swap = G_028C70_COMP_SWAP(cb->cb_color_info);
has_alpha = !G_028C74_FORCE_DST_ALPHA_1_GFX6(cb->cb_color_attrib);
has_alpha = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11
? !G_028C74_FORCE_DST_ALPHA_1_GFX11(cb->cb_color_attrib)
: !G_028C74_FORCE_DST_ALPHA_1_GFX6(cb->cb_color_attrib);
} else {
VkFormat fmt = cmd_buffer->state.pass->attachments[idx].format;
format = radv_translate_colorformat(fmt);
@@ -1706,7 +1710,10 @@ radv_emit_primitive_restart_enable(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_GE_MULTI_PRIM_IB_RESET_EN,
d->primitive_restart_enable);
} else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
d->primitive_restart_enable);
} else {

46
src/amd/vulkan/radv_device.c
View File

@@ -5507,11 +5507,16 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv
}
}
return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(independent_128b_blocks);
uint32_t result = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
if (device->physical_device->rad_info.gfx_level >= GFX11)
result |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(independent_128b_blocks);
else
result |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(independent_128b_blocks);
return result;
}
void
@@ -5530,7 +5535,10 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
memset(cb, 0, sizeof(*cb));
/* Intensity is implemented as Red, so treat it that way. */
cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1);
if (device->physical_device->rad_info.gfx_level >= GFX11)
cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1_GFX11(desc->swizzle[3] == PIPE_SWIZZLE_1);
else
cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1);
va = radv_buffer_get_va(iview->image->bo) + iview->image->offset;
@@ -5619,8 +5627,11 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
if (iview->image->info.samples > 1) {
unsigned log_samples = util_logbase2(iview->image->info.samples);
cb->cb_color_attrib |=
S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS_GFX6(log_samples);
if (device->physical_device->rad_info.gfx_level >= GFX11)
cb->cb_color_attrib |= S_028C74_NUM_FRAGMENTS_GFX11(log_samples);
else
cb->cb_color_attrib |=
S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS_GFX6(log_samples);
}
if (radv_image_has_fmask(iview->image)) {
@@ -5660,12 +5671,18 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
->color_is_int8 = true;
#endif
cb->cb_color_info =
S_028C70_FORMAT_GFX6(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) |
S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) |
S_028C70_BLEND_BYPASS(blend_bypass) | S_028C70_SIMPLE_FLOAT(1) |
S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM &&
ntype != V_028C70_NUMBER_SRGB && format != V_028C70_COLOR_8_24 &&
format != V_028C70_COLOR_24_8) |
S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian);
S_028C70_NUMBER_TYPE(ntype);
if (device->physical_device->rad_info.gfx_level >= GFX11)
cb->cb_color_info |= S_028C70_FORMAT_GFX11(format);
else
cb->cb_color_info |= S_028C70_FORMAT_GFX6(format) | S_028C70_ENDIAN(endian);
if (radv_image_has_fmask(iview->image)) {
cb->cb_color_info |= S_028C70_COMPRESSION(1);
if (device->physical_device->rad_info.gfx_level == GFX6) {
@@ -5694,7 +5711,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
!(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
if (radv_dcc_enabled(iview->image, iview->base_mip) && !iview->disable_dcc_mrt)
if (radv_dcc_enabled(iview->image, iview->base_mip) && !iview->disable_dcc_mrt &&
device->physical_device->rad_info.gfx_level < GFX11)
cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
@@ -5717,9 +5735,9 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
if (device->physical_device->rad_info.gfx_level >= GFX10) {
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
S_028EE0_RESOURCE_LEVEL(1);
cb->cb_color_attrib3 |=
S_028EE0_MIP0_DEPTH(mip0_depth) | S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
S_028EE0_RESOURCE_LEVEL(device->physical_device->rad_info.gfx_level >= GFX11 ? 0 : 1);
} else {
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
cb->cb_color_attrib |=

4
src/amd/vulkan/radv_meta_fast_clear.c
View File

@@ -373,7 +373,9 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli
},
&(struct radv_graphics_pipeline_create_info){
.use_rectlist = true,
.custom_blend_mode = V_028808_CB_DCC_DECOMPRESS_GFX8,
.custom_blend_mode = device->physical_device->rad_info.gfx_level >= GFX11
? V_028808_CB_DCC_DECOMPRESS_GFX11
: V_028808_CB_DCC_DECOMPRESS_GFX8,
},
&device->meta_state.alloc, &device->meta_state.fast_clear_flush.dcc_decompress_pipeline);
if (result != VK_SUCCESS)

57
src/amd/vulkan/radv_pipeline.c
View File

@@ -352,7 +352,7 @@ si_translate_blend_function(VkBlendOp op)
}
static uint32_t
si_translate_blend_factor(VkBlendFactor factor)
si_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor)
{
switch (factor) {
case VK_BLEND_FACTOR_ZERO:
@@ -378,21 +378,26 @@ si_translate_blend_factor(VkBlendFactor factor)
case VK_BLEND_FACTOR_CONSTANT_COLOR:
return V_028780_BLEND_CONSTANT_COLOR_GFX6;
case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11
: V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
case VK_BLEND_FACTOR_CONSTANT_ALPHA:
return V_028780_BLEND_CONSTANT_ALPHA_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11
: V_028780_BLEND_CONSTANT_ALPHA_GFX6;
case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11
: V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
return V_028780_BLEND_SRC_ALPHA_SATURATE;
case VK_BLEND_FACTOR_SRC1_COLOR:
return V_028780_BLEND_SRC1_COLOR_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11 : V_028780_BLEND_SRC1_COLOR_GFX6;
case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
return V_028780_BLEND_INV_SRC1_COLOR_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11
: V_028780_BLEND_INV_SRC1_COLOR_GFX6;
case VK_BLEND_FACTOR_SRC1_ALPHA:
return V_028780_BLEND_SRC1_ALPHA_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11 : V_028780_BLEND_SRC1_ALPHA_GFX6;
case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
return V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11
: V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
default:
return 0;
}
@@ -692,6 +697,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
radv_pipeline_get_multisample_state(pipeline, pCreateInfo);
struct radv_blend_state blend = {0};
unsigned cb_color_control = 0;
const enum amd_gfx_level gfx_level = pipeline->device->physical_device->rad_info.gfx_level;
int i;
if (vkblend) {
@@ -808,13 +814,13 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
blend_cntl |= S_028780_ENABLE(1);
blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(gfx_level, srcRGB));
blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(gfx_level, dstRGB));
if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(gfx_level, srcA));
blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(gfx_level, dstA));
}
blend.cb_blend_control[i] = blend_cntl;
@@ -5603,9 +5609,20 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) |
S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(ngg_state->max_gsprims) |
S_03096C_VERT_GRP_SIZE(ngg_state->enable_vertex_grouping ? ngg_state->hw_max_esverts : 256) | /* 256 = disable vertex grouping */
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX11) {
ge_cntl = S_03096C_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
S_03096C_VERT_GRP_SIZE(ngg_state->enable_vertex_grouping
? ngg_state->hw_max_esverts
: 256) | /* 256 = disable vertex grouping */
S_03096C_BREAK_PRIMGRP_AT_EOI(break_wave_at_eoi) |
S_03096C_PRIM_GRP_SIZE_GFX11(256);
} else {
ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(ngg_state->max_gsprims) |
S_03096C_VERT_GRP_SIZE(ngg_state->enable_vertex_grouping
? ngg_state->hw_max_esverts
: 256) | /* 256 = disable vertex grouping */
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
}
/* Bug workaround for a possible hang with non-tessellation cases.
* Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
@@ -5627,7 +5644,14 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
ac_compute_late_alloc(&pipeline->device->physical_device->rad_info, true, shader->info.has_ngg_culling,
shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX11) {
/* TODO: figure out how S_00B204_CU_EN_GFX11 interacts with ac_set_reg_cu_en */
gfx10_set_sh_reg_idx3(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F));
gfx10_set_sh_reg_idx3(
cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
S_00B204_CU_EN_GFX11(0x1) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
} else if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
ac_set_reg_cu_en(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F),
C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info,
@@ -6574,6 +6598,7 @@ radv_pipeline_init_extra(struct radv_pipeline *pipeline,
if (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS_GFX8 ||
extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS_GFX11 ||
extra->custom_blend_mode == V_028808_CB_RESOLVE) {
/* According to the CB spec states, CB_SHADER_MASK should be set to enable writes to all four
* channels of MRT0.

3
src/amd/vulkan/radv_sqtt.c
View File

@@ -381,6 +381,9 @@ radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs,
static void
radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit)
{
if (device->physical_device->rad_info.gfx_level >= GFX11)
return; /* not needed */
if (device->physical_device->rad_info.gfx_level >= GFX10) {
radeon_set_uconfig_reg(cs, R_037390_RLC_PERFMON_CLK_CNTL,
S_037390_PERFMON_CLOCK_STATE(inhibit));

43
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -275,9 +275,11 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
radeon_set_context_reg(cs, R_028038_DB_DFSM_CONTROL,
S_028038_PUNCHOUT_MODE(V_028038_FORCE_OFF) |
S_028038_POPS_DRAIN_PS_ON_OVERLAP(1));
if (physical_device->rad_info.gfx_level < GFX11) {
radeon_set_context_reg(
cs, R_028038_DB_DFSM_CONTROL,
S_028038_PUNCHOUT_MODE(V_028038_FORCE_OFF) | S_028038_POPS_DRAIN_PS_ON_OVERLAP(1));
}
} else if (physical_device->rad_info.gfx_level == GFX9) {
radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
@@ -401,6 +403,9 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
/* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
unsigned meta_write_policy, meta_read_policy;
unsigned no_alloc = device->physical_device->rad_info.gfx_level >= GFX11
? V_02807C_CACHE_NOA_GFX11
: V_02807C_CACHE_NOA_GFX10;
/* TODO: investigate whether LRU improves performance on other chips too */
if (physical_device->rad_info.max_render_backends <= 4) {
@@ -408,25 +413,33 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
} else {
meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
meta_read_policy = V_02807C_CACHE_NOA_GFX10; /* don't cache reads */
meta_read_policy = no_alloc; /* don't cache reads */
}
radeon_set_context_reg(
cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_HTILE_WR_POLICY(meta_write_policy) |
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_GFX10) | S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_GFX10) |
S_02807C_HTILE_RD_POLICY(meta_read_policy));
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_Z_RD_POLICY(no_alloc) |
S_02807C_S_RD_POLICY(no_alloc) | S_02807C_HTILE_RD_POLICY(meta_read_policy));
radeon_set_context_reg(
cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
S_028410_CMASK_WR_POLICY(meta_write_policy) | S_028410_FMASK_WR_POLICY(meta_write_policy) |
S_028410_DCC_WR_POLICY_GFX10(meta_write_policy) |
S_028410_COLOR_WR_POLICY_GFX10(V_028410_CACHE_STREAM) |
S_028410_CMASK_RD_POLICY(meta_read_policy) |
S_028410_FMASK_RD_POLICY(meta_read_policy) | S_028410_DCC_RD_POLICY(meta_read_policy) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10));
uint32_t gl2_cc;
if (device->physical_device->rad_info.gfx_level >= GFX11) {
gl2_cc = S_028410_DCC_WR_POLICY_GFX11(meta_write_policy) |
S_028410_COLOR_WR_POLICY_GFX11(V_028410_CACHE_STREAM) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX11);
} else {
gl2_cc = S_028410_CMASK_WR_POLICY(meta_write_policy) |
S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM) |
S_028410_DCC_WR_POLICY_GFX10(meta_write_policy) |
S_028410_COLOR_WR_POLICY_GFX10(V_028410_CACHE_STREAM) |
S_028410_CMASK_RD_POLICY(meta_read_policy) |
S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_GFX10) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10);
}
radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
gl2_cc | S_028410_DCC_RD_POLICY(meta_read_policy));
radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4);