From e8fb4b82e92042198f1a8b853f91e28069aeabb5 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 19 Jun 2024 11:38:40 +0200 Subject: [PATCH] radv: fix emitting indirect descriptor sets in the DGC prepare shader NIR_DEBUG=validate_ssa_dominance failed because dgc_cs_emit() weren't actually in the if. Fixes: 33a849e004d ("radv: emit indirect sets for indirect compute pipelines with DGC") Signed-off-by: Samuel Pitoiset Part-of: --- .../vulkan/radv_device_generated_commands.c | 29 ++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 85ba912ad60..2a4a4955ea9 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -1510,6 +1510,23 @@ dgc_emit_draw_mesh_tasks(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *d /** * Emit VK_INDIRECT_COMMANDS_TOKEN_TYPE_PIPELINE_NV. */ +static void +dgc_emit_indirect_sets(struct dgc_cmdbuf *cs, nir_def *pipeline_va) +{ + nir_builder *b = cs->b; + + nir_def *indirect_desc_sets_sgpr = load_metadata32(b, indirect_desc_sets_sgpr); + nir_push_if(b, nir_ine_imm(b, indirect_desc_sets_sgpr, 0)); + { + dgc_cs_begin(cs); + dgc_cs_emit_imm(PKT3(PKT3_SET_SH_REG, 1, 0)); + dgc_cs_emit(indirect_desc_sets_sgpr); + dgc_cs_emit(load_param32(b, indirect_desc_sets_va)); + dgc_cs_end(); + } + nir_pop_if(b, NULL); +} + static void dgc_emit_bind_pipeline(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_variable *upload_offset) { @@ -1539,18 +1556,10 @@ dgc_emit_bind_pipeline(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_variable dgc_cs_emit(load_metadata32(b, block_size_x)); dgc_cs_emit(load_metadata32(b, block_size_y)); dgc_cs_emit(load_metadata32(b, block_size_z)); - - nir_def *indirect_desc_sets_sgpr = load_metadata32(b, indirect_desc_sets_sgpr); - nir_push_if(b, nir_ine_imm(b, indirect_desc_sets_sgpr, 0)); - { - dgc_cs_emit_imm(PKT3(PKT3_SET_SH_REG, 1, 0)); - dgc_cs_emit(indirect_desc_sets_sgpr); - dgc_cs_emit(load_param32(b, indirect_desc_sets_va)); - } - nir_pop_if(b, NULL); - dgc_cs_end(); + dgc_emit_indirect_sets(cs, pipeline_va); + nir_store_var(b, upload_offset, nir_iadd_imm(b, nir_load_var(b, upload_offset), MAX_SETS * 4), 0x1); }