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radv: fix emitting indirect descriptor sets in the DGC prepare shader

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NIR_DEBUG=validate_ssa_dominance failed because dgc_cs_emit() weren't
actually in the if.

Fixes: 33a849e004 ("radv: emit indirect sets for indirect compute pipelines with DGC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29782>
This commit is contained in:
Samuel Pitoiset
2024-06-19 11:38:40 +02:00
committed by Marge Bot
parent 6a2309b676
commit e8fb4b82e9
1 changed files with 19 additions and 10 deletions
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29
src/amd/vulkan/radv_device_generated_commands.c
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@@ -1510,6 +1510,23 @@ dgc_emit_draw_mesh_tasks(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *d
/**
* Emit VK_INDIRECT_COMMANDS_TOKEN_TYPE_PIPELINE_NV.
*/
static void
dgc_emit_indirect_sets(struct dgc_cmdbuf *cs, nir_def *pipeline_va)
{
nir_builder *b = cs->b;
nir_def *indirect_desc_sets_sgpr = load_metadata32(b, indirect_desc_sets_sgpr);
nir_push_if(b, nir_ine_imm(b, indirect_desc_sets_sgpr, 0));
{
dgc_cs_begin(cs);
dgc_cs_emit_imm(PKT3(PKT3_SET_SH_REG, 1, 0));
dgc_cs_emit(indirect_desc_sets_sgpr);
dgc_cs_emit(load_param32(b, indirect_desc_sets_va));
dgc_cs_end();
}
nir_pop_if(b, NULL);
}
static void
dgc_emit_bind_pipeline(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_variable *upload_offset)
{
@@ -1539,18 +1556,10 @@ dgc_emit_bind_pipeline(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_variable
dgc_cs_emit(load_metadata32(b, block_size_x));
dgc_cs_emit(load_metadata32(b, block_size_y));
dgc_cs_emit(load_metadata32(b, block_size_z));
nir_def *indirect_desc_sets_sgpr = load_metadata32(b, indirect_desc_sets_sgpr);
nir_push_if(b, nir_ine_imm(b, indirect_desc_sets_sgpr, 0));
{
dgc_cs_emit_imm(PKT3(PKT3_SET_SH_REG, 1, 0));
dgc_cs_emit(indirect_desc_sets_sgpr);
dgc_cs_emit(load_param32(b, indirect_desc_sets_va));
}
nir_pop_if(b, NULL);
dgc_cs_end();
dgc_emit_indirect_sets(cs, pipeline_va);
nir_store_var(b, upload_offset, nir_iadd_imm(b, nir_load_var(b, upload_offset), MAX_SETS * 4), 0x1);
}