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intel/compiler: Re-prefix non-logical surface opcodes with VEC4

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The scalar back-end uses SHADER_OPCODE_SEND for all surface messages so
we no longer need the non-logical opcodes there.  Prefix them VEC4 so
it's clear that they're only used by the vec4 back-end.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Jason Ekstrand
2019-02-21 10:41:59 -06:00
parent 95ae400abc
commit e8f863e718
10 changed files with 25 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/intel/compiler/brw_eu_defines.h
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@@ -402,12 +402,12 @@ enum opcode {
* Source 4: [required] Opcode-specific control immediate, same as source 2 * Source 4: [required] Opcode-specific control immediate, same as source 2
* of the matching non-LOGICAL opcode. * of the matching non-LOGICAL opcode.
*/ */
SHADER_OPCODE_UNTYPED_ATOMIC, VEC4_OPCODE_UNTYPED_ATOMIC,
SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL, SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
SHADER_OPCODE_UNTYPED_SURFACE_READ, VEC4_OPCODE_UNTYPED_SURFACE_READ,
SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
SHADER_OPCODE_UNTYPED_SURFACE_WRITE, VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
/** /**

9
src/intel/compiler/brw_fs.cpp
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@@ -221,9 +221,6 @@ fs_inst::is_send_from_grf() const
case FS_OPCODE_INTERPOLATE_AT_SAMPLE: case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_URB_WRITE_SIMD8: case SHADER_OPCODE_URB_WRITE_SIMD8:
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
@@ -280,9 +277,6 @@ fs_inst::is_control_source(unsigned arg) const
case SHADER_OPCODE_TG4: case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET: case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO: case SHADER_OPCODE_SAMPLEINFO:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
return arg == 1 || arg == 2; return arg == 1 || arg == 2;
case SHADER_OPCODE_SEND: case SHADER_OPCODE_SEND:
@@ -953,9 +947,6 @@ fs_inst::size_read(int arg) const
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case SHADER_OPCODE_URB_READ_SIMD8: case SHADER_OPCODE_URB_READ_SIMD8:
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case FS_OPCODE_INTERPOLATE_AT_SAMPLE: case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
if (arg == 0) if (arg == 0)

12
src/intel/compiler/brw_fs_copy_propagation.cpp
View File

@@ -709,18 +709,6 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
} }
break; break;
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
/* We only propagate into the surface argument of the
* instruction. Everything else goes through LOAD_PAYLOAD.
*/
if (i == 1) {
inst->src[i] = val;
progress = true;
}
break;
case FS_OPCODE_FB_WRITE_LOGICAL: case FS_OPCODE_FB_WRITE_LOGICAL:
/* The stencil and omask sources of FS_OPCODE_FB_WRITE_LOGICAL are /* The stencil and omask sources of FS_OPCODE_FB_WRITE_LOGICAL are
* bit-cast using a strided region so they cannot be immediates. * bit-cast using a strided region so they cannot be immediates.

1
src/intel/compiler/brw_fs_dead_code_eliminate.cpp
View File

@@ -53,7 +53,6 @@ static bool
can_omit_write(const fs_inst *inst) can_omit_write(const fs_inst *inst)
{ {
switch (inst->opcode) { switch (inst->opcode) {
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:

6
src/intel/compiler/brw_schedule_instructions.cpp
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@@ -367,13 +367,13 @@ schedule_node::set_latency_gen7(bool is_haswell)
latency = 50; latency = 50;
break; break;
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
/* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */ /* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
latency = 14000; latency = 14000;
break; break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
/* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */ /* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
latency = is_haswell ? 300 : 600; latency = is_haswell ? 300 : 600;
break; break;

12
src/intel/compiler/brw_shader.cpp
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@@ -276,17 +276,17 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case SHADER_OPCODE_SHADER_TIME_ADD: case SHADER_OPCODE_SHADER_TIME_ADD:
return "shader_time_add"; return "shader_time_add";
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
return "untyped_atomic"; return "untyped_atomic";
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
return "untyped_atomic_logical"; return "untyped_atomic_logical";
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
return "untyped_atomic_float_logical"; return "untyped_atomic_float_logical";
case SHADER_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
return "untyped_surface_read"; return "untyped_surface_read";
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
return "untyped_surface_read_logical"; return "untyped_surface_read_logical";
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
return "untyped_surface_write"; return "untyped_surface_write";
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
return "untyped_surface_write_logical"; return "untyped_surface_write_logical";
@@ -1001,11 +1001,11 @@ backend_instruction::has_side_effects() const
case SHADER_OPCODE_SEND: case SHADER_OPCODE_SEND:
return send_has_side_effects; return send_has_side_effects;
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
@@ -1040,7 +1040,7 @@ backend_instruction::is_volatile() const
case SHADER_OPCODE_SEND: case SHADER_OPCODE_SEND:
return send_is_volatile; return send_is_volatile;
case SHADER_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:

12
src/intel/compiler/brw_vec4.cpp
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@@ -153,9 +153,9 @@ vec4_instruction::is_send_from_grf()
switch (opcode) { switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD: case SHADER_OPCODE_SHADER_TIME_ADD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case VEC4_OPCODE_URB_READ: case VEC4_OPCODE_URB_READ:
case TCS_OPCODE_URB_WRITE: case TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT: case TCS_OPCODE_RELEASE_INPUT:
@@ -209,9 +209,9 @@ vec4_instruction::size_read(unsigned arg) const
{ {
switch (opcode) { switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD: case SHADER_OPCODE_SHADER_TIME_ADD:
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case TCS_OPCODE_URB_WRITE: case TCS_OPCODE_URB_WRITE:
if (arg == 0) if (arg == 0)
return mlen * REG_SIZE; return mlen * REG_SIZE;

2
src/intel/compiler/brw_vec4_copy_propagation.cpp
View File

@@ -190,7 +190,7 @@ try_constant_propagate(const struct gen_device_info *devinfo,
inst->src[arg] = value; inst->src[arg] = value;
return true; return true;
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
if (arg == 1) { if (arg == 1) {
inst->src[arg] = value; inst->src[arg] = value;
return true; return true;

6
src/intel/compiler/brw_vec4_generator.cpp
View File

@@ -1863,20 +1863,20 @@ generate_code(struct brw_codegen *p,
prog_data->base.binding_table.shader_time_start); prog_data->base.binding_table.shader_time_start);
break; break;
case SHADER_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
assert(src[2].file == BRW_IMMEDIATE_VALUE); assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen, brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
!inst->dst.is_null(), inst->header_size); !inst->dst.is_null(), inst->header_size);
break; break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
assert(!inst->header_size); assert(!inst->header_size);
assert(src[2].file == BRW_IMMEDIATE_VALUE); assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen, brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
src[2].ud); src[2].ud);
break; break;
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE); assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_write(p, src[0], src[1], inst->mlen, brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
src[2].ud, inst->header_size); src[2].ud, inst->header_size);

6
src/intel/compiler/brw_vec4_surface_builder.cpp
View File

@@ -146,7 +146,7 @@ namespace brw {
unsigned dims, unsigned size, unsigned dims, unsigned size,
brw_predicate pred) brw_predicate pred)
{ {
return emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_READ, src_reg(), return emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_READ, src_reg(),
emit_insert(bld, addr, dims, true), 1, emit_insert(bld, addr, dims, true), 1,
src_reg(), 0, src_reg(), 0,
surface, size, 1, pred); surface, size, 1, pred);
@@ -165,7 +165,7 @@ namespace brw {
{ {
const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 || const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
bld.shader->devinfo->is_haswell); bld.shader->devinfo->is_haswell);
emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(), emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(),
emit_insert(bld, addr, dims, has_simd4x2), emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims, has_simd4x2 ? 1 : dims,
emit_insert(bld, src, size, has_simd4x2), emit_insert(bld, src, size, has_simd4x2),
@@ -204,7 +204,7 @@ namespace brw {
swizzle(src1, BRW_SWIZZLE_XXXX)); swizzle(src1, BRW_SWIZZLE_XXXX));
} }
return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC, src_reg(), return emit_send(bld, VEC4_OPCODE_UNTYPED_ATOMIC, src_reg(),
emit_insert(bld, addr, dims, has_simd4x2), emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims, has_simd4x2 ? 1 : dims,
emit_insert(bld, src_reg(srcs), size, has_simd4x2), emit_insert(bld, src_reg(srcs), size, has_simd4x2),