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intel/compiler: Re-prefix non-logical surface opcodes with VEC4

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The scalar back-end uses SHADER_OPCODE_SEND for all surface messages so
we no longer need the non-logical opcodes there.  Prefix them VEC4 so
it's clear that they're only used by the vec4 back-end.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Jason Ekstrand
2019-02-21 10:41:59 -06:00
parent 95ae400abc
commit e8f863e718
10 changed files with 25 additions and 47 deletions
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6
src/intel/compiler/brw_schedule_instructions.cpp
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@@ -367,13 +367,13 @@ schedule_node::set_latency_gen7(bool is_haswell)
latency = 50;
break;
case SHADER_OPCODE_UNTYPED_ATOMIC:
case VEC4_OPCODE_UNTYPED_ATOMIC:
/* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
latency = 14000;
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
/* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
latency = is_haswell ? 300 : 600;
break;