OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/compiler: detect if atomic load store operations are used

Browse Source 
Patch adds a new arg and modifies existing calls from i965, anv
pass NULL but iris stores this information for later use.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
This commit is contained in:
Tapani Pälli
2020-03-06 08:59:16 +02:00
committed by Marge Bot
parent 6dd654ba41
commit e8f0483ec4
7 changed files with 16 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/iris/iris_context.h
View File

@@ -361,6 +361,9 @@ struct iris_uncompiled_shader {
bool needs_edge_flag;
/* Whether shader uses atomic operations. */
bool uses_atomic_load_store;
/** Constant data scraped from the shader by nir_opt_large_constants */
struct pipe_resource *const_data;

3
src/gallium/drivers/iris/iris_program.c
View File

@@ -2131,7 +2131,8 @@ iris_create_uncompiled_shader(struct pipe_context *ctx,
brw_preprocess_nir(screen->compiler, nir, NULL);
NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo);
NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo,
&ish->uses_atomic_load_store);
NIR_PASS_V(nir, iris_lower_storage_image_derefs);
nir_sweep(nir);

3
src/intel/compiler/brw_compiler.h
View File

@@ -679,6 +679,9 @@ struct brw_stage_prog_data {
*/
uint32_t *param;
uint32_t *pull_param;
/* Whether shader uses atomic operations. */
bool uses_atomic_load_store;
};
static inline uint32_t *

3
src/intel/compiler/brw_nir.h
View File

@@ -121,7 +121,8 @@ void brw_nir_lower_fs_outputs(nir_shader *nir);
bool brw_nir_lower_conversions(nir_shader *nir);
bool brw_nir_lower_image_load_store(nir_shader *nir,
const struct gen_device_info *devinfo);
const struct gen_device_info *devinfo,
bool *uses_atomic_load_store);
void brw_nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin,
nir_ssa_def *index);
void brw_nir_rewrite_bindless_image_intrinsic(nir_intrinsic_instr *intrin,

5
src/intel/compiler/brw_nir_lower_image_load_store.c
View File

@@ -680,7 +680,8 @@ lower_image_size_instr(nir_builder *b,
bool
brw_nir_lower_image_load_store(nir_shader *shader,
const struct gen_device_info *devinfo)
const struct gen_device_info *devinfo,
bool *uses_atomic_load_store)
{
bool progress = false;
@@ -718,6 +719,8 @@ brw_nir_lower_image_load_store(nir_shader *shader,
case nir_intrinsic_image_deref_atomic_xor:
case nir_intrinsic_image_deref_atomic_exchange:
case nir_intrinsic_image_deref_atomic_comp_swap:
if (uses_atomic_load_store)
*uses_atomic_load_store = true;
if (lower_image_atomic_instr(&b, devinfo, intrin))
progress = true;
break;

2
src/intel/vulkan/anv_pipeline.c
View File

@@ -692,7 +692,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
NIR_PASS_V(nir, brw_nir_lower_image_load_store, compiler->devinfo);
NIR_PASS_V(nir, brw_nir_lower_image_load_store, compiler->devinfo, NULL);
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
nir_address_format_64bit_global);

2
src/mesa/drivers/dri/i965/brw_program.c
View File

@@ -186,7 +186,7 @@ brw_nir_lower_resources(nir_shader *nir, struct gl_shader_program *shader_prog,
prog->info.textures_used = prog->nir->info.textures_used;
prog->info.textures_used_by_txf = prog->nir->info.textures_used_by_txf;
NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo);
NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo, NULL);
if (prog->nir->info.stage == MESA_SHADER_COMPUTE &&
shader_prog->data->spirv) {