r600g: add cs tracing infrastructure for lockup pin pointing
It's a build time option you need to set R600_TRACE_CS to 1 and it will print to stderr all cs along as cs trace point value which gave last offset into a cs process by the GPU. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
@@ -27,6 +27,7 @@
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#include "r600d.h"
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#include "util/u_memory.h"
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#include <errno.h>
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#include <unistd.h>
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/* Get backends mask */
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void r600_get_backend_mask(struct r600_context *ctx)
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@@ -369,6 +370,11 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
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for (i = 0; i < R600_NUM_ATOMS; i++) {
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if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
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num_dw += ctx->atoms[i]->num_dw;
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#if R600_TRACE_CS
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if (ctx->screen->trace_bo) {
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num_dw += R600_TRACE_CS_DWORDS;
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}
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#endif
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}
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}
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@@ -376,6 +382,11 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
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/* The upper-bound of how much space a draw command would take. */
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num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
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#if R600_TRACE_CS
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if (ctx->screen->trace_bo) {
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num_dw += R600_TRACE_CS_DWORDS;
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}
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#endif
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}
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/* Count in queries_suspend. */
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@@ -717,7 +728,37 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
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}
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/* Flush the CS. */
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#if R600_TRACE_CS
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if (ctx->screen->trace_bo) {
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struct r600_screen *rscreen = ctx->screen;
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unsigned i;
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for (i = 0; i < cs->cdw; i++) {
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fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]);
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}
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rscreen->cs_count++;
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}
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#endif
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ctx->ws->cs_flush(ctx->cs, flags);
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#if R600_TRACE_CS
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if (ctx->screen->trace_bo) {
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struct r600_screen *rscreen = ctx->screen;
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unsigned i;
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for (i = 0; i < 10; i++) {
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usleep(5);
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if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) {
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break;
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}
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}
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if (i == 10) {
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fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
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rscreen->trace_ptr[1], rscreen->trace_ptr[0]);
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} else {
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fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5);
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}
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}
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#endif
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r600_begin_new_cs(ctx);
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}
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@@ -29,8 +29,9 @@
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#include "r600_pipe.h"
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/* the number of CS dwords for flushing and drawing */
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#define R600_MAX_FLUSH_CS_DWORDS 12
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#define R600_MAX_DRAW_CS_DWORDS 34
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#define R600_MAX_FLUSH_CS_DWORDS 12
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#define R600_MAX_DRAW_CS_DWORDS 34
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#define R600_TRACE_CS_DWORDS 7
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/* these flags are used in register flags and added into block flags */
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#define REG_FLAG_NEED_BO 1
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@@ -723,6 +723,12 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
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rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
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pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
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}
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#if R600_TRACE_CS
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if (rscreen->trace_bo) {
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rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
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pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
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}
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#endif
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pipe_mutex_destroy(rscreen->fences.mutex);
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rscreen->ws->destroy(rscreen->ws);
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@@ -1042,5 +1048,19 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
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rscreen->global_pool = compute_memory_pool_new(rscreen);
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#if R600_TRACE_CS
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rscreen->cs_count = 0;
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if (rscreen->info.drm_minor >= 28) {
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rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
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PIPE_BIND_CUSTOM,
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PIPE_USAGE_STAGING,
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4096);
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if (rscreen->trace_bo) {
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rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
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PIPE_TRANSFER_UNSYNCHRONIZED);
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}
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}
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#endif
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return &rscreen->screen;
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}
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@@ -37,6 +37,8 @@
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#define R600_NUM_ATOMS 37
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#define R600_TRACE_CS 0
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#define R600_MAX_USER_CONST_BUFFERS 1
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#define R600_MAX_DRIVER_CONST_BUFFERS 2
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#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
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@@ -235,6 +237,11 @@ struct r600_screen {
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* XXX: Not sure if this is the best place for global_pool. Also,
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* it's not thread safe, so it won't work with multiple contexts. */
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struct compute_memory_pool *global_pool;
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#if R600_TRACE_CS
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struct r600_resource *trace_bo;
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uint32_t *trace_ptr;
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unsigned cs_count;
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#endif
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};
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struct r600_pipe_sampler_view {
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@@ -533,10 +540,19 @@ static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
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cs->cdw += cb->num_dw;
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}
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#if R600_TRACE_CS
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void r600_trace_emit(struct r600_context *rctx);
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#endif
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static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
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{
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atom->emit(rctx, atom);
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atom->dirty = false;
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#if R600_TRACE_CS
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if (rctx->screen->trace_bo) {
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r600_trace_emit(rctx);
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}
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#endif
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}
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static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
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@@ -1328,6 +1328,12 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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(info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
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}
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#if R600_TRACE_CS
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if (rctx->screen->trace_bo) {
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r600_trace_emit(rctx);
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}
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#endif
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/* Set the depth buffer as dirty. */
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if (rctx->framebuffer.state.zsbuf) {
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struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
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@@ -1620,3 +1626,23 @@ void r600_init_common_state_functions(struct r600_context *rctx)
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rctx->context.set_stream_output_targets = r600_set_so_targets;
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rctx->context.draw_vbo = r600_draw_vbo;
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}
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#if R600_TRACE_CS
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void r600_trace_emit(struct r600_context *rctx)
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{
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struct r600_screen *rscreen = rctx->screen;
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struct radeon_winsys_cs *cs = rctx->cs;
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uint64_t va;
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uint32_t reloc;
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va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
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reloc = r600_context_bo_reloc(rctx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
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r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
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r600_write_value(cs, va & 0xFFFFFFFFUL);
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r600_write_value(cs, (va >> 32UL) & 0xFFUL);
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r600_write_value(cs, cs->cdw);
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r600_write_value(cs, rscreen->cs_count);
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r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
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r600_write_value(cs, reloc);
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}
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#endif
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