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intel/elk: Remove IADD3 opcode

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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
This commit is contained in:
Caio Oliveira
2024-02-09 22:21:35 -08:00
committed by Marge Bot
parent d1049408b5
commit e8c4104362
16 changed files with 1 additions and 119 deletions
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1
src/intel/compiler/elk/elk_compiler.c
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@@ -119,7 +119,6 @@ elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->lower_bitfield_reverse = devinfo->ver < 7;
nir_options->lower_find_lsb = devinfo->ver < 7;
nir_options->lower_ifind_msb = devinfo->ver < 7;
nir_options->has_iadd3 = devinfo->verx10 >= 125;
nir_options->lower_int64_options = int64_options;
nir_options->lower_doubles_options = fp64_options;

1
src/intel/compiler/elk/elk_eu.c
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@@ -733,7 +733,6 @@ static const struct elk_opcode_desc opcode_descs[] = {
{ ELK_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) },
{ ELK_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL },
{ ELK_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL },
{ ELK_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) },
{ ELK_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) },
{ ELK_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) },
{ ELK_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) },

1
src/intel/compiler/elk/elk_eu.h
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@@ -241,7 +241,6 @@ ALU3(CSEL)
ALU1(F32TO16)
ALU1(F16TO32)
ALU2(ADD)
ALU3(ADD3)
ALU2(AVG)
ALU2(MUL)
ALU1(FRC)

1
src/intel/compiler/elk/elk_eu_emit.c
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@@ -1076,7 +1076,6 @@ ALU1(FBL)
ALU1(CBIT)
ALU2(ADDC)
ALU2(SUBB)
ALU3(ADD3)
elk_inst *
elk_MOV(struct elk_codegen *p, struct elk_reg dest, struct elk_reg src0)

1
src/intel/compiler/elk/elk_eu_opcodes.h
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@@ -79,7 +79,6 @@ enum elk_opcode {
ELK_OPCODE_SUBB, /**< Gfx7+ */
ELK_OPCODE_SAD2,
ELK_OPCODE_SADA2,
ELK_OPCODE_ADD3, /* Gen12+ only */
ELK_OPCODE_DP4,
ELK_OPCODE_DPH,
ELK_OPCODE_DP3,

41
src/intel/compiler/elk/elk_eu_validate.c
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@@ -2221,47 +2221,6 @@ instruction_restrictions(const struct elk_isa_info *isa,
}
}
if (elk_inst_opcode(isa, inst) == ELK_OPCODE_ADD3) {
const enum elk_reg_type dst_type = inst_dst_type(isa, inst);
ERROR_IF(dst_type != ELK_REGISTER_TYPE_D &&
dst_type != ELK_REGISTER_TYPE_UD &&
dst_type != ELK_REGISTER_TYPE_W &&
dst_type != ELK_REGISTER_TYPE_UW,
"Destination must be integer D, UD, W, or UW type.");
for (unsigned i = 0; i < 3; i++) {
enum elk_reg_type src_type;
switch (i) {
case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break;
case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break;
case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break;
default: unreachable("invalid src");
}
ERROR_IF(src_type != ELK_REGISTER_TYPE_D &&
src_type != ELK_REGISTER_TYPE_UD &&
src_type != ELK_REGISTER_TYPE_W &&
src_type != ELK_REGISTER_TYPE_UW,
"Source must be integer D, UD, W, or UW type.");
if (i == 0) {
if (elk_inst_3src_a1_src0_is_imm(devinfo, inst)) {
ERROR_IF(src_type != ELK_REGISTER_TYPE_W &&
src_type != ELK_REGISTER_TYPE_UW,
"Immediate source must be integer W or UW type.");
}
} else if (i == 2) {
if (elk_inst_3src_a1_src2_is_imm(devinfo, inst)) {
ERROR_IF(src_type != ELK_REGISTER_TYPE_W &&
src_type != ELK_REGISTER_TYPE_UW,
"Immediate source must be integer W or UW type.");
}
}
}
}
if (elk_inst_opcode(isa, inst) == ELK_OPCODE_OR ||
elk_inst_opcode(isa, inst) == ELK_OPCODE_AND ||
elk_inst_opcode(isa, inst) == ELK_OPCODE_XOR ||

1
src/intel/compiler/elk/elk_fs.cpp
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@@ -4723,7 +4723,6 @@ get_lowered_simd_width(const elk_fs_visitor *shader, const elk_fs_inst *inst)
case ELK_OPCODE_SAD2:
case ELK_OPCODE_MAD:
case ELK_OPCODE_LRP:
case ELK_OPCODE_ADD3:
case ELK_FS_OPCODE_PACK:
case ELK_SHADER_OPCODE_SEL_EXEC:
case ELK_SHADER_OPCODE_CLUSTER_BROADCAST:

1
src/intel/compiler/elk/elk_fs_builder.h
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@@ -617,7 +617,6 @@ namespace elk {
}
ALU2(ADD)
ALU3(ADD3)
ALU2_ACC(ADDC)
ALU2(AND)
ALU2(ASR)

5
src/intel/compiler/elk/elk_fs_combine_constants.cpp
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@@ -1038,10 +1038,6 @@ supports_src_as_imm(const struct intel_device_info *devinfo, const elk_fs_inst *
return false;
switch (inst->opcode) {
case ELK_OPCODE_ADD3:
/* ADD3 only exists on Gfx12.5+. */
return true;
case ELK_OPCODE_MAD:
/* Integer types can always mix sizes. Floating point types can mix
* sizes on Gfx12. On Gfx12.5, floating point sources must all be HF or
@@ -1357,7 +1353,6 @@ elk_fs_visitor::opt_combine_constants()
break;
case ELK_OPCODE_ADD3:
case ELK_OPCODE_MAD: {
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != IMM)

33
src/intel/compiler/elk/elk_fs_copy_propagation.cpp
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@@ -1104,30 +1104,6 @@ try_constant_propagate(const elk_compiler *compiler, elk_fs_inst *inst,
}
break;
case ELK_OPCODE_ADD3:
/* add3 can have a single imm16 source. Proceed if the source type is
* already W or UW or the value can be coerced to one of those types.
*/
if (val.type == ELK_REGISTER_TYPE_W || val.type == ELK_REGISTER_TYPE_UW)
; /* Nothing to do. */
else if (val.ud <= 0xffff)
val = elk_imm_uw(val.ud);
else if (val.d >= -0x8000 && val.d <= 0x7fff)
val = elk_imm_w(val.d);
else
break;
if (arg == 2) {
inst->src[arg] = val;
progress = true;
} else if (inst->src[2].file != IMM) {
inst->src[arg] = inst->src[2];
inst->src[2] = val;
progress = true;
}
break;
case ELK_OPCODE_CMP:
case ELK_OPCODE_IF:
if (arg == 1) {
@@ -1307,15 +1283,6 @@ opt_copy_propagation_local(const elk_compiler *compiler, linear_ctx *lin_ctx,
if (instruction_progress) {
progress = true;
/* ADD3 can only have the immediate as src0. */
if (inst->opcode == ELK_OPCODE_ADD3) {
if (inst->src[2].file == IMM) {
const auto src0 = inst->src[0];
inst->src[0] = inst->src[2];
inst->src[2] = src0;
}
}
/* If only one of the sources of a 2-source, commutative instruction (e.g.,
* AND) is immediate, it must be src1. If both are immediate, opt_algebraic
* should fold it away.

5
src/intel/compiler/elk/elk_fs_generator.cpp
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@@ -1816,11 +1816,6 @@ elk_fs_generator::generate_code(const elk_cfg_t *cfg, int dispatch_width,
elk_LRP(p, dst, src[0], src[1], src[2]);
break;
case ELK_OPCODE_ADD3:
assert(devinfo->verx10 >= 125);
elk_ADD3(p, dst, src[0], src[1], src[2]);
break;
case ELK_OPCODE_FRC:
elk_FRC(p, dst, src[0]);
break;

18
src/intel/compiler/elk/elk_fs_nir.cpp
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@@ -1278,10 +1278,6 @@ fs_nir_emit_alu(nir_to_elk_state &ntb, nir_alu_instr *instr,
inst = bld.ADD(result, op[0], op[1]);
break;
case nir_op_iadd3:
inst = bld.ADD3(result, op[0], op[1], op[2]);
break;
case nir_op_iadd_sat:
case nir_op_uadd_sat:
inst = bld.ADD(result, op[0], op[1]);
@@ -4682,20 +4678,6 @@ try_rebuild_resource(nir_to_elk_state &ntb, const elk::fs_builder &bld, nir_def
src0.file != IMM ? src1 : src0);
break;
}
case nir_op_iadd3: {
elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD);
elk_fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst;
elk_fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst;
elk_fs_reg src2 = ntb.resource_insts[alu->src[2].src.ssa->index]->dst;
assert(src0.file != BAD_FILE && src1.file != BAD_FILE && src2.file != BAD_FILE);
assert(src0.type == ELK_REGISTER_TYPE_UD);
ntb.resource_insts[def->index] =
ubld8.ADD3(dst,
src1.file == IMM ? src1 : src0,
src1.file == IMM ? src0 : src1,
src2);
break;
}
case nir_op_ushr: {
elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD);
elk_fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst;

6
src/intel/compiler/elk/elk_gram.y
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@@ -273,9 +273,6 @@ i965_asm_ternary_instruction(int opcode,
case ELK_OPCODE_BFI2:
elk_BFI2(p, dest, src0, src1, src2);
break;
case ELK_OPCODE_ADD3:
elk_ADD3(p, dest, src0, src1, src2);
break;
default:
fprintf(stderr, "Unsupported ternary opcode\n");
}
@@ -388,7 +385,7 @@ add_label(struct elk_codegen *p, const char* label_name, enum instr_label_type t
%token <string> JUMP_LABEL_TARGET
/* opcodes */
%token <integer> ADD ADD3 ADDC AND ASR AVG
%token <integer> ADD ADDC AND ASR AVG
%token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
%token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
%token <integer> DIM DO DP2 DP3 DP4 DPH
@@ -951,7 +948,6 @@ ternaryopcodes:
| BFI2
| LRP
| MAD
| ADD3
;
/* Wait instruction */

1
src/intel/compiler/elk/elk_ir_performance.cpp
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@@ -379,7 +379,6 @@ namespace {
case ELK_OPCODE_MOV:
case ELK_OPCODE_CMP:
case ELK_OPCODE_ADD:
case ELK_OPCODE_ADD3:
case ELK_OPCODE_MUL:
case ELK_SHADER_OPCODE_MOV_RELOC_IMM:
case ELK_VEC4_OPCODE_MOV_FOR_SCRATCH:

1
src/intel/compiler/elk/elk_lex.l
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@@ -52,7 +52,6 @@ null { BEGIN(REG); return NULL_TOKEN; }
/* Opcodes */
add { yylval.integer = ELK_OPCODE_ADD; return ADD; }
add3 { yylval.integer = ELK_OPCODE_ADD3; return ADD3; }
addc { yylval.integer = ELK_OPCODE_ADDC; return ADDC; }
and { yylval.integer = ELK_OPCODE_AND; return AND; }
asr { yylval.integer = ELK_OPCODE_ASR; return ASR; }

3
src/intel/compiler/elk/elk_shader.cpp
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@@ -821,7 +821,6 @@ elk_backend_instruction::is_commutative() const
case ELK_OPCODE_OR:
case ELK_OPCODE_XOR:
case ELK_OPCODE_ADD:
case ELK_OPCODE_ADD3:
case ELK_OPCODE_MUL:
case ELK_SHADER_OPCODE_MULH:
return true;
@@ -944,7 +943,6 @@ elk_backend_instruction::can_do_saturate() const
{
switch (opcode) {
case ELK_OPCODE_ADD:
case ELK_OPCODE_ADD3:
case ELK_OPCODE_ASR:
case ELK_OPCODE_AVG:
case ELK_OPCODE_CSEL:
@@ -990,7 +988,6 @@ elk_backend_instruction::can_do_cmod() const
{
switch (opcode) {
case ELK_OPCODE_ADD:
case ELK_OPCODE_ADD3:
case ELK_OPCODE_ADDC:
case ELK_OPCODE_AND:
case ELK_OPCODE_ASR: