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intel: Rename GENx keyword to GFXx

Browse Source 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+\)/GFX\1/g"

Exclude the changes to modifiers:
grep -E "I915_.*GFX" -rIl $SEARCH_PATH | xargs sed -ie "s/\(I915_.*\)GFX/\1GEN/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat
2021-03-29 16:02:30 -07:00
committed by Marge Bot
parent 1d296484b4
commit e7e55af4d6
42 changed files with 239 additions and 239 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/compiler/brw_compiler.h
View File

@@ -577,7 +577,7 @@ struct brw_image_param {
/**
* Binding table index for the first gfx6 SOL binding.
*/
#define BRW_GEN6_SOL_BINDING_START 0
#define BRW_GFX6_SOL_BINDING_START 0
/**
* Stride in bytes between shader_time entries.

12
src/intel/compiler/brw_eu_defines.h
View File

@@ -480,9 +480,9 @@ enum opcode {
*/
FS_OPCODE_SCHEDULING_FENCE,
SHADER_OPCODE_GEN4_SCRATCH_READ,
SHADER_OPCODE_GEN4_SCRATCH_WRITE,
SHADER_OPCODE_GEN7_SCRATCH_READ,
SHADER_OPCODE_GFX4_SCRATCH_READ,
SHADER_OPCODE_GFX4_SCRATCH_WRITE,
SHADER_OPCODE_GFX7_SCRATCH_READ,
SHADER_OPCODE_SCRATCH_HEADER,
@@ -584,8 +584,8 @@ enum opcode {
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
FS_OPCODE_SET_SAMPLE_ID,
FS_OPCODE_PACK_HALF_2x16_SPLIT,
@@ -595,7 +595,7 @@ enum opcode {
VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_PULL_CONSTANT_LOAD_GFX7,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,

18
src/intel/compiler/brw_fs.cpp
View File

@@ -252,8 +252,8 @@ fs_inst::is_control_source(unsigned arg) const
{
switch (opcode) {
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return arg == 0;
case SHADER_OPCODE_BROADCAST:
@@ -317,7 +317,7 @@ fs_inst::is_payload(unsigned arg) const
case SHADER_OPCODE_BARRIER:
return arg == 0;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
return arg == 1;
case SHADER_OPCODE_SEND:
@@ -988,7 +988,7 @@ fs_inst::size_read(int arg) const
return 1;
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
/* The payload is actually stored in src1 */
if (arg == 1)
return mlen * REG_SIZE;
@@ -1174,11 +1174,11 @@ fs_inst::implied_mrf_writes() const
case FS_OPCODE_REP_FB_WRITE:
return src[0].file == BAD_FILE ? 0 : 2;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
return 1;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return mlen;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return mlen;
default:
unreachable("not reached");
@@ -3799,7 +3799,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
ubld.group(1, 0).MOV(component(payload, 2),
brw_imm_ud(inst->src[1].ud / 16));
inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7;
inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7;
inst->src[1] = payload;
inst->header_size = 1;
inst->mlen = 1;
@@ -6103,7 +6103,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
bld.MOV(byte_offset(payload, REG_SIZE), inst->src[1]);
inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4;
inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4;
inst->resize_sources(1);
inst->base_mrf = payload.nr;
inst->header_size = 1;

2
src/intel/compiler/brw_fs_copy_propagation.cpp
View File

@@ -523,7 +523,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
}
if (has_source_modifiers &&
inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE)
return false;
/* Some instructions implemented in the generator backend, such as

10
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -2331,17 +2331,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
generate_ddy(inst, dst, src[0]);
break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
generate_scratch_write(inst, src[0]);
spill_count++;
break;
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
generate_scratch_read(inst, dst);
fill_count++;
break;
case SHADER_OPCODE_GEN7_SCRATCH_READ:
case SHADER_OPCODE_GFX7_SCRATCH_READ:
generate_scratch_read_gfx7(inst, dst);
fill_count++;
break;
@@ -2379,13 +2379,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
send_count++;
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
assert(inst->force_writemask_all);
generate_uniform_pull_constant_load_gfx7(inst, dst, src[0], src[1]);
send_count++;
break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
generate_varying_pull_constant_load_gfx4(inst, dst, src[0]);
send_count++;
break;

10
src/intel/compiler/brw_fs_reg_allocate.cpp
View File

@@ -704,8 +704,8 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* message as source. So as we will have an overlap for sure, we create
* an interference between destination and grf127.
*/
if ((inst->opcode == SHADER_OPCODE_GEN7_SCRATCH_READ ||
inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ) &&
if ((inst->opcode == SHADER_OPCODE_GFX7_SCRATCH_READ ||
inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ) &&
inst->dst.file == VGRF)
ra_add_node_interference(g, first_vgrf_node + inst->dst.nr,
grf127_send_hack_node);
@@ -921,10 +921,10 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
* the address as part of the message header, so we're better off
* using plain old oword block reads.
*/
unspill_inst = bld.emit(SHADER_OPCODE_GEN7_SCRATCH_READ, dst);
unspill_inst = bld.emit(SHADER_OPCODE_GFX7_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset;
} else {
unspill_inst = bld.emit(SHADER_OPCODE_GEN4_SCRATCH_READ, dst);
unspill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset;
unspill_inst->base_mrf = spill_base_mrf(bld.shader);
unspill_inst->mlen = 1; /* header contains offset */
@@ -972,7 +972,7 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
0 /* not a render target */,
false /* send_commit_msg */);
} else {
spill_inst = bld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
spill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_WRITE,
bld.null_reg_f(), src);
spill_inst->offset = spill_offset;
spill_inst->mlen = 1 + reg_size; /* header, value */

12
src/intel/compiler/brw_ir_performance.cpp
View File

@@ -903,7 +903,7 @@ namespace {
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16 /* XXX */,
8 /* XXX */, 750 /* XXX */, 0, 0,
2 /* XXX */, 0);
@@ -948,9 +948,9 @@ namespace {
abort();
}
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GEN7_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX7_SCRATCH_READ:
return calculate_desc(info, unit_dp_dc, 2, 0, 0, 0, 8 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
@@ -989,12 +989,12 @@ namespace {
abort();
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
return calculate_desc(info, unit_dp_cc, 2, 0, 0, 0, 16 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16,
8, 750, 0, 0, 2, 0);

4
src/intel/compiler/brw_ir_vec4.h
View File

@@ -354,8 +354,8 @@ public:
case VS_OPCODE_PULL_CONSTANT_LOAD:
case GS_OPCODE_SET_PRIMITIVE_ID:
case GS_OPCODE_GET_INSTANCE_ID:
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return true;
default:
return false;

6
src/intel/compiler/brw_schedule_instructions.cpp
View File

@@ -322,9 +322,9 @@ schedule_node::set_latency_gfx7(bool is_haswell)
latency = 100;
break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
case VS_OPCODE_PULL_CONSTANT_LOAD:
/* testing using varying-index pull constants:
*
@@ -355,7 +355,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
latency = 200;
break;
case SHADER_OPCODE_GEN7_SCRATCH_READ:
case SHADER_OPCODE_GFX7_SCRATCH_READ:
/* Testing a load from offset 0, that had been previously written:
*
* send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };

14
src/intel/compiler/brw_shader.cpp
View File

@@ -359,11 +359,11 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case FS_OPCODE_PACK:
return "pack";
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
return "gfx4_scratch_read";
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return "gfx4_scratch_write";
case SHADER_OPCODE_GEN7_SCRATCH_READ:
case SHADER_OPCODE_GFX7_SCRATCH_READ:
return "gfx7_scratch_read";
case SHADER_OPCODE_SCRATCH_HEADER:
return "scratch_header";
@@ -441,9 +441,9 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
return "uniform_pull_const_gfx7";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return "varying_pull_const_gfx4";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
return "varying_pull_const_logical";
@@ -468,7 +468,7 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
return "vs_urb_write";
case VS_OPCODE_PULL_CONSTANT_LOAD:
return "pull_constant_load";
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
return "pull_constant_load_gfx7";
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
@@ -1100,7 +1100,7 @@ backend_instruction::has_side_effects() const
case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:

16
src/intel/compiler/brw_vec4.cpp
View File

@@ -151,7 +151,7 @@ vec4_instruction::is_send_from_grf() const
{
switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
case VEC4_OPCODE_UNTYPED_ATOMIC:
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
@@ -215,7 +215,7 @@ vec4_instruction::size_read(unsigned arg) const
if (arg == 0)
return mlen * REG_SIZE;
break;
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
if (arg == 1)
return mlen * REG_SIZE;
break;
@@ -274,7 +274,7 @@ bool
vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
{
switch (opcode) {
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
case VEC4_OPCODE_DOUBLE_TO_F32:
case VEC4_OPCODE_DOUBLE_TO_D32:
case VEC4_OPCODE_DOUBLE_TO_U32:
@@ -284,7 +284,7 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
case VEC4_OPCODE_SET_LOW_32BIT:
case VEC4_OPCODE_SET_HIGH_32BIT:
case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
@@ -349,9 +349,9 @@ vec4_instruction::implied_mrf_writes() const
return 1;
case VS_OPCODE_PULL_CONSTANT_LOAD:
return 2;
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
return 2;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return 3;
case GS_OPCODE_URB_WRITE:
case GS_OPCODE_URB_WRITE_ALLOCATE:
@@ -2179,8 +2179,8 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
{
/* Do not split some instructions that require special handling */
switch (inst->opcode) {
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return inst->exec_size;
default:
break;

2
src/intel/compiler/brw_vec4_copy_propagation.cpp
View File

@@ -366,7 +366,7 @@ try_copy_propagate(const struct gen_device_info *devinfo,
return false;
if (has_source_modifiers &&
(inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE ||
(inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE ||
inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT))
return false;

8
src/intel/compiler/brw_vec4_generator.cpp
View File

@@ -506,7 +506,7 @@ generate_gs_svb_write(struct brw_codegen *p,
final_write ? src1 : brw_null_reg(), /* dest == src1 */
1, /* msg_reg_nr */
dst, /* src0 == previous dst */
BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */
BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
final_write); /* send_commit_msg */
/* Finally, wait for the write commit to occur so that we can proceed to
@@ -1774,12 +1774,12 @@ generate_code(struct brw_codegen *p,
send_count++;
break;
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
generate_scratch_read(p, inst, dst, src[0]);
fill_count++;
break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
generate_scratch_write(p, inst, dst, src[0], src[1]);
spill_count++;
break;
@@ -1789,7 +1789,7 @@ generate_code(struct brw_codegen *p,
send_count++;
break;
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]);
send_count++;
break;

8
src/intel/compiler/brw_vec4_reg_allocate.cpp
View File

@@ -330,8 +330,8 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
* other registers (that won't read/write scratch_reg) do not stop us from
* reusing scratch_reg for this instruction.
*/
if (prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE ||
prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ)
if (prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE ||
prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ)
continue;
/* If the previous instruction does not write to scratch_reg, then check
@@ -466,8 +466,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
loop_scale /= 10;
break;
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
for (int i = 0; i < 3; i++) {
if (inst->src[i].file == VGRF)
no_spill[inst->src[i].nr] = true;

6
src/intel/compiler/brw_vec4_visitor.cpp
View File

@@ -257,7 +257,7 @@ vec4_visitor::SCRATCH_READ(const dst_reg &dst, const src_reg &index)
{
vec4_instruction *inst;
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ,
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GFX4_SCRATCH_READ,
dst, index);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver) + 1;
inst->mlen = 2;
@@ -271,7 +271,7 @@ vec4_visitor::SCRATCH_WRITE(const dst_reg &dst, const src_reg &src,
{
vec4_instruction *inst;
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GFX4_SCRATCH_WRITE,
dst, src, index);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver);
inst->mlen = 3;
@@ -752,7 +752,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
else
emit(pull);
pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GFX7,
dst,
surf_index,
src_reg(grf_offset));