diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h index 72db58e8e98..ed24c09ec73 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h @@ -34,7 +34,7 @@ extern "C" { // Used to resolve corner case #define DPP_SFRB(field_name, reg_name, post_fix) .field_name = reg_name##_##field_name##post_fix -#define DPP_REG_LIST_VPE10(id) \ +#define DPP_REG_LIST_VPE10_COMMON(id) \ SRIDFVL(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_FORMAT_CONTROL, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_FCNV_FP_BIAS_R, VPCNVC_CFG, id), \ @@ -48,7 +48,6 @@ extern "C" { SRIDFVL(VPCNVC_COLOR_KEYER_RED, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_COLOR_KEYER_GREEN, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_COLOR_KEYER_BLUE, VPCNVC_CFG, id), \ - SRIDFVL(VPCNVC_ALPHA_2BIT_LUT, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_PRE_DEALPHA, VPCNVC_CFG, id), SRIDFVL(VPCNVC_PRE_CSC_MODE, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_PRE_CSC_C11_C12, VPCNVC_CFG, id), \ SRIDFVL(VPCNVC_PRE_CSC_C13_C14, VPCNVC_CFG, id), \ @@ -82,10 +81,7 @@ extern "C" { SRIDFVL(VPCM_POST_CSC_CONTROL, VPCM, id), SRIDFVL(VPCM_POST_CSC_C11_C12, VPCM, id), \ SRIDFVL(VPCM_POST_CSC_C13_C14, VPCM, id), SRIDFVL(VPCM_POST_CSC_C21_C22, VPCM, id), \ SRIDFVL(VPCM_POST_CSC_C23_C24, VPCM, id), SRIDFVL(VPCM_POST_CSC_C31_C32, VPCM, id), \ - SRIDFVL(VPCM_POST_CSC_C33_C34, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_CONTROL, VPCM, id), \ - SRIDFVL(VPCM_GAMUT_REMAP_C11_C12, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C13_C14, VPCM, id), \ - SRIDFVL(VPCM_GAMUT_REMAP_C21_C22, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C23_C24, VPCM, id), \ - SRIDFVL(VPCM_GAMUT_REMAP_C31_C32, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C33_C34, VPCM, id), \ + SRIDFVL(VPCM_POST_CSC_C33_C34, VPCM, id), \ SRIDFVL(VPCM_BIAS_CR_R, VPCM, id), SRIDFVL(VPCM_BIAS_Y_G_CB_B, VPCM, id), \ SRIDFVL(VPCM_GAMCOR_CONTROL, VPCM, id), SRIDFVL(VPCM_GAMCOR_LUT_INDEX, VPCM, id), \ SRIDFVL(VPCM_GAMCOR_LUT_DATA, VPCM, id), SRIDFVL(VPCM_GAMCOR_LUT_CONTROL, VPCM, id), \ @@ -126,9 +122,17 @@ extern "C" { SRIDFVL(VPCM_GAMCOR_RAMA_REGION_32_33, VPCM, id), SRIDFVL(VPCM_HDR_MULT_COEF, VPCM, id), \ SRIDFVL(VPCM_MEM_PWR_CTRL, VPCM, id), SRIDFVL(VPCM_MEM_PWR_STATUS, VPCM, id), \ SRIDFVL(VPCM_DEALPHA, VPCM, id), SRIDFVL(VPCM_COEF_FORMAT, VPCM, id), \ - SRIDFVL(VPDPP_CONTROL, VPDPP_TOP, id), SRIDFVL(VPDPP_CRC_CTRL, VPDPP_TOP, id), + SRIDFVL(VPDPP_CONTROL, VPDPP_TOP, id), SRIDFVL(VPDPP_CRC_CTRL, VPDPP_TOP, id) -#define DPP_FIELD_LIST_VPE10(post_fix) \ +#define DPP_REG_LIST_VPE10(id) \ + DPP_REG_LIST_VPE10_COMMON(id), \ + SRIDFVL(VPCNVC_ALPHA_2BIT_LUT, VPCNVC_CFG, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_CONTROL, VPCM, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_C11_C12, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C13_C14, VPCM, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_C21_C22, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C23_C24, VPCM, id), \ + SRIDFVL(VPCM_GAMUT_REMAP_C31_C32, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C33_C34, VPCM, id) + +#define DPP_FIELD_LIST_VPE10_COMMON(post_fix) \ SFRB(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_SURFACE_PIXEL_FORMAT, post_fix), \ SFRB(FORMAT_EXPANSION_MODE, VPCNVC_FORMAT_CONTROL, post_fix), \ SFRB(FORMAT_CNV16, VPCNVC_FORMAT_CONTROL, post_fix), \ @@ -154,10 +158,6 @@ extern "C" { SFRB(COLOR_KEYER_GREEN_HIGH, VPCNVC_COLOR_KEYER_GREEN, post_fix), \ SFRB(COLOR_KEYER_BLUE_LOW, VPCNVC_COLOR_KEYER_BLUE, post_fix), \ SFRB(COLOR_KEYER_BLUE_HIGH, VPCNVC_COLOR_KEYER_BLUE, post_fix), \ - SFRB(ALPHA_2BIT_LUT0, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ - SFRB(ALPHA_2BIT_LUT1, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ - SFRB(ALPHA_2BIT_LUT2, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ - SFRB(ALPHA_2BIT_LUT3, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ SFRB(PRE_DEALPHA_EN, VPCNVC_PRE_DEALPHA, post_fix), \ SFRB(PRE_DEALPHA_ABLND_EN, VPCNVC_PRE_DEALPHA, post_fix), \ SFRB(PRE_CSC_MODE, VPCNVC_PRE_CSC_MODE, post_fix), \ @@ -265,20 +265,6 @@ extern "C" { SFRB(VPCM_POST_CSC_C32, VPCM_POST_CSC_C31_C32, post_fix), \ SFRB(VPCM_POST_CSC_C33, VPCM_POST_CSC_C33_C34, post_fix), \ SFRB(VPCM_POST_CSC_C34, VPCM_POST_CSC_C33_C34, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_MODE, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_MODE_CURRENT, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C11, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C12, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C13, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C14, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C21, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C22, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C23, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C24, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C31, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C32, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C33, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_C34, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ SFRB(VPCM_BIAS_CR_R, VPCM_BIAS_CR_R, post_fix), \ SFRB(VPCM_BIAS_Y_G, VPCM_BIAS_Y_G_CB_B, post_fix), \ SFRB(VPCM_BIAS_CB_B, VPCM_BIAS_Y_G_CB_B, post_fix), \ @@ -402,7 +388,6 @@ extern "C" { SFRB(VPCM_DEALPHA_ABLND, VPCM_DEALPHA, post_fix), \ SFRB(VPCM_BIAS_FORMAT, VPCM_COEF_FORMAT, post_fix), \ SFRB(VPCM_POST_CSC_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \ - SFRB(VPCM_GAMUT_REMAP_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \ SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix), \ SFRB(VPECLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ SFRB(VPECLK_G_DYN_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ @@ -419,7 +404,29 @@ extern "C" { SFRB(VPDPP_CRC_PIX_FORMAT_SEL, VPDPP_CRC_CTRL, post_fix), \ SFRB(VPDPP_CRC_MASK, VPDPP_CRC_CTRL, post_fix) -#define DPP_REG_VARIABLE_LIST_VPE10 \ +#define DPP_FIELD_LIST_VPE10(post_fix) \ + DPP_FIELD_LIST_VPE10_COMMON(post_fix), \ + SFRB(ALPHA_2BIT_LUT0, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(ALPHA_2BIT_LUT1, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(ALPHA_2BIT_LUT2, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(ALPHA_2BIT_LUT3, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_MODE, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_MODE_CURRENT, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C11, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C12, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C13, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C14, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C21, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C22, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C23, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C24, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C31, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C32, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C33, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_C34, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ + SFRB(VPCM_GAMUT_REMAP_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix) + +#define DPP_REG_VARIABLE_LIST_VPE10_COMMON \ reg_id_val VPCNVC_SURFACE_PIXEL_FORMAT; \ reg_id_val VPCNVC_FORMAT_CONTROL; \ reg_id_val VPCNVC_FCNV_FP_BIAS_R; \ @@ -433,7 +440,6 @@ extern "C" { reg_id_val VPCNVC_COLOR_KEYER_RED; \ reg_id_val VPCNVC_COLOR_KEYER_GREEN; \ reg_id_val VPCNVC_COLOR_KEYER_BLUE; \ - reg_id_val VPCNVC_ALPHA_2BIT_LUT; \ reg_id_val VPCNVC_PRE_DEALPHA; \ reg_id_val VPCNVC_PRE_CSC_MODE; \ reg_id_val VPCNVC_PRE_CSC_C11_C12; \ @@ -483,13 +489,6 @@ extern "C" { reg_id_val VPCM_POST_CSC_C23_C24; \ reg_id_val VPCM_POST_CSC_C31_C32; \ reg_id_val VPCM_POST_CSC_C33_C34; \ - reg_id_val VPCM_GAMUT_REMAP_CONTROL; \ - reg_id_val VPCM_GAMUT_REMAP_C11_C12; \ - reg_id_val VPCM_GAMUT_REMAP_C13_C14; \ - reg_id_val VPCM_GAMUT_REMAP_C21_C22; \ - reg_id_val VPCM_GAMUT_REMAP_C23_C24; \ - reg_id_val VPCM_GAMUT_REMAP_C31_C32; \ - reg_id_val VPCM_GAMUT_REMAP_C33_C34; \ reg_id_val VPCM_BIAS_CR_R; \ reg_id_val VPCM_BIAS_Y_G_CB_B; \ reg_id_val VPCM_GAMCOR_CONTROL; \ @@ -539,6 +538,17 @@ extern "C" { reg_id_val VPDPP_CONTROL; \ reg_id_val VPDPP_CRC_CTRL; +#define DPP_REG_VARIABLE_LIST_VPE10 \ + DPP_REG_VARIABLE_LIST_VPE10_COMMON \ + reg_id_val VPCNVC_ALPHA_2BIT_LUT; \ + reg_id_val VPCM_GAMUT_REMAP_CONTROL; \ + reg_id_val VPCM_GAMUT_REMAP_C11_C12; \ + reg_id_val VPCM_GAMUT_REMAP_C13_C14; \ + reg_id_val VPCM_GAMUT_REMAP_C21_C22; \ + reg_id_val VPCM_GAMUT_REMAP_C23_C24; \ + reg_id_val VPCM_GAMUT_REMAP_C31_C32; \ + reg_id_val VPCM_GAMUT_REMAP_C33_C34; + #define DPP_FIELD_VARIABLE_LIST_VPE10(type) \ type VPCNVC_SURFACE_PIXEL_FORMAT; \ type FORMAT_EXPANSION_MODE; \