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radv: fix a synchronization issue with non-preprocessed DGC with task shader

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We need to make sure that the DGC ACE IB will wait for the DGC
prepare shader before the execution starts. When DGC is preprocessed
the synchronization is already correct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
This commit is contained in:
Samuel Pitoiset
2024-06-26 16:26:41 +02:00
committed by Marge Bot
parent 74713469e1
commit e6aee84265
1 changed files with 14 additions and 1 deletions
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15
src/amd/vulkan/radv_cmd_buffer.c
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@@ -631,7 +631,8 @@ radv_gang_barrier(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_
/* Add stage flush only when necessary. */
if (src_stage_mask & (VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT |
VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT))
VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT |
VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV))
cmd_buffer->gang.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
/* Block task shaders when we have to wait for CP DMA on the GFX cmdbuf. */
@@ -11575,6 +11576,18 @@ radv_CmdExecuteGeneratedCommandsNV(VkCommandBuffer commandBuffer, VkBool32 isPre
}
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2;
if (!compute) {
struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);
/* Make sure the DGC ACE IB will wait for the DGC prepare shader before the execution
* starts.
*/
if (radv_pipeline_has_stage(graphics_pipeline, MESA_SHADER_TASK)) {
radv_gang_barrier(cmd_buffer, VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV,
VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT);
}
}
}
if (compute) {