r300-gallium: vs: Add scalar setup, RSQ.
Icky icky icky icky. Icky icky, icky icky. Icky.
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@@ -135,6 +135,8 @@ static uint32_t r300_vs_op(unsigned op)
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case TGSI_OPCODE_MOV:
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case TGSI_OPCODE_MOV:
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case TGSI_OPCODE_SWZ:
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case TGSI_OPCODE_SWZ:
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return R300_VE_ADD;
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return R300_VE_ADD;
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case TGSI_OPCODE_RSQ:
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return R300_PVS_DST_MATH_INST | R300_ME_RECIP_DX;
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case TGSI_OPCODE_MAD:
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case TGSI_OPCODE_MAD:
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return R300_PVS_DST_MACRO_INST | R300_PVS_MACRO_OP_2CLK_MADD;
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return R300_PVS_DST_MACRO_INST | R300_PVS_MACRO_OP_2CLK_MADD;
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default:
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default:
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@@ -158,12 +160,30 @@ static uint32_t r300_vs_swiz(struct tgsi_full_src_register* reg)
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}
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}
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}
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}
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/* XXX icky icky icky icky */
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static uint32_t r300_vs_scalar_swiz(struct tgsi_full_src_register* reg)
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{
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if (reg->SrcRegister.Extended) {
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return reg->SrcRegisterExtSwz.ExtSwizzleX |
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(reg->SrcRegisterExtSwz.ExtSwizzleX << 3) |
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(reg->SrcRegisterExtSwz.ExtSwizzleX << 6) |
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(reg->SrcRegisterExtSwz.ExtSwizzleX << 9);
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} else {
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return reg->SrcRegister.SwizzleX |
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(reg->SrcRegister.SwizzleX << 3) |
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(reg->SrcRegister.SwizzleX << 6) |
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(reg->SrcRegister.SwizzleX << 9);
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}
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}
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/* XXX scalar stupidity */
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static void r300_vs_emit_inst(struct r300_vertex_shader* vs,
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static void r300_vs_emit_inst(struct r300_vertex_shader* vs,
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struct r300_vs_asm* assembler,
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struct r300_vs_asm* assembler,
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struct tgsi_full_src_register* src,
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struct tgsi_full_src_register* src,
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struct tgsi_full_dst_register* dst,
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struct tgsi_full_dst_register* dst,
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unsigned op,
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unsigned op,
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unsigned count)
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unsigned count,
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boolean is_scalar)
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{
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{
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int i = vs->instruction_count;
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int i = vs->instruction_count;
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vs->instructions[i].inst0 = R300_PVS_DST_OPCODE(r300_vs_op(op)) |
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vs->instructions[i].inst0 = R300_PVS_DST_OPCODE(r300_vs_op(op)) |
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@@ -190,7 +210,9 @@ static void r300_vs_emit_inst(struct r300_vertex_shader* vs,
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R300_PVS_SRC_REG_TYPE(r300_vs_src_type(assembler,
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R300_PVS_SRC_REG_TYPE(r300_vs_src_type(assembler,
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&src[0].SrcRegister)) |
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&src[0].SrcRegister)) |
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R300_PVS_SRC_OFFSET(src[0].SrcRegister.Index) |
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R300_PVS_SRC_OFFSET(src[0].SrcRegister.Index) |
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R300_PVS_SRC_SWIZZLE(r300_vs_swiz(&src[0]));
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/* XXX the icky, it burns */
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R300_PVS_SRC_SWIZZLE(is_scalar ? r300_vs_scalar_swiz(&src[0])
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: r300_vs_swiz(&src[0]));
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break;
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break;
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}
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}
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vs->instruction_count++;
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vs->instruction_count++;
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@@ -201,11 +223,16 @@ static void r300_vs_instruction(struct r300_vertex_shader* vs,
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struct tgsi_full_instruction* inst)
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struct tgsi_full_instruction* inst)
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{
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{
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switch (inst->Instruction.Opcode) {
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switch (inst->Instruction.Opcode) {
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case TGSI_OPCODE_RSQ:
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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1, TRUE);
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break;
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case TGSI_OPCODE_ADD:
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case TGSI_OPCODE_ADD:
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case TGSI_OPCODE_MUL:
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case TGSI_OPCODE_MUL:
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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2);
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2, FALSE);
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break;
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break;
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case TGSI_OPCODE_DP3:
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case TGSI_OPCODE_DP3:
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/* Set alpha swizzle to zero for src0 and src1 */
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/* Set alpha swizzle to zero for src0 and src1 */
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@@ -235,19 +262,19 @@ static void r300_vs_instruction(struct r300_vertex_shader* vs,
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case TGSI_OPCODE_DP4:
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case TGSI_OPCODE_DP4:
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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2);
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2, FALSE);
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break;
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break;
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case TGSI_OPCODE_MOV:
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case TGSI_OPCODE_MOV:
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case TGSI_OPCODE_SWZ:
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case TGSI_OPCODE_SWZ:
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inst->FullSrcRegisters[1] = r300_constant_zero;
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inst->FullSrcRegisters[1] = r300_constant_zero;
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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2);
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2, FALSE);
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break;
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break;
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case TGSI_OPCODE_MAD:
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case TGSI_OPCODE_MAD:
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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r300_vs_emit_inst(vs, assembler, inst->FullSrcRegisters,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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&inst->FullDstRegisters[0], inst->Instruction.Opcode,
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3);
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3, FALSE);
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break;
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break;
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case TGSI_OPCODE_END:
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case TGSI_OPCODE_END:
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break;
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break;
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@@ -35,6 +35,8 @@
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# define R300_VE_DOT_PRODUCT 1
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# define R300_VE_DOT_PRODUCT 1
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# define R300_VE_MULTIPLY 2
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# define R300_VE_MULTIPLY 2
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# define R300_VE_ADD 3
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# define R300_VE_ADD 3
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#define R300_PVS_DST_MATH_INST (1 << 6)
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# define R300_ME_RECIP_DX 6
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#define R300_PVS_DST_MACRO_INST (1 << 7)
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#define R300_PVS_DST_MACRO_INST (1 << 7)
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# define R300_PVS_MACRO_OP_2CLK_MADD 0
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# define R300_PVS_MACRO_OP_2CLK_MADD 0
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#define R300_PVS_DST_REG_TYPE(x) ((x) << 8)
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#define R300_PVS_DST_REG_TYPE(x) ((x) << 8)
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