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intel/compiler: Initial bits for DPAS instruction

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v2: Add brw_ir_performance.cpp and brw_fs_generator.cpp changes. Fix
overlapping register allocation (via has_source_and_destination_hazard). Fix
incorrect destination register file encoding.

v3: Prevent lower_regioning from trying to "fix" DPAS sources.

v4: Add instruction latency information for scheduling and perf
estimates.

v5: Remove all mention of DPASW. Suggested by Curro and Caio. Update
the comment in fs_inst::has_source_and_destination_hazard. Suggested
by Caio.

v6: Add some comments near the src2 calculation in
fs_inst::size_read. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
This commit is contained in:
Ian Romanick
2023-09-20 12:42:24 -07:00
parent 3a35f8b29b
commit e666872c75
14 changed files with 297 additions and 3 deletions
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4
src/intel/compiler/brw_fs_lower_regioning.cpp
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@@ -253,8 +253,10 @@ namespace {
has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst,
unsigned i)
{
if (is_send(inst) || inst->is_math() || inst->is_control_source(i))
if (is_send(inst) || inst->is_math() || inst->is_control_source(i) ||
inst->opcode == BRW_OPCODE_DPAS) {
return false;
}
/* Empirical testing shows that Broadwell has a bug affecting half-float
* MAD instructions when any of its sources has a non-zero offset, such