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intel/compiler: Initial bits for DPAS instruction

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v2: Add brw_ir_performance.cpp and brw_fs_generator.cpp changes. Fix
overlapping register allocation (via has_source_and_destination_hazard). Fix
incorrect destination register file encoding.

v3: Prevent lower_regioning from trying to "fix" DPAS sources.

v4: Add instruction latency information for scheduling and perf
estimates.

v5: Remove all mention of DPASW. Suggested by Curro and Caio. Update
the comment in fs_inst::has_source_and_destination_hazard. Suggested
by Caio.

v6: Add some comments near the src2 calculation in
fs_inst::size_read. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
This commit is contained in:
Ian Romanick
2023-09-20 12:42:24 -07:00
parent 3a35f8b29b
commit e666872c75
14 changed files with 297 additions and 3 deletions
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5
src/intel/compiler/brw_eu_validate.c
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@@ -687,7 +687,10 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
return error_msg;
if (devinfo->ver >= 11) {
if (num_sources == 3) {
/* A register type of B or UB for DPAS actually means 4 bytes packed into
* a D or UD, so it is allowed.
*/
if (num_sources == 3 && brw_inst_opcode(isa, inst) != BRW_OPCODE_DPAS) {
ERROR_IF(brw_reg_type_to_size(brw_inst_3src_a1_src1_type(devinfo, inst)) == 1 ||
brw_reg_type_to_size(brw_inst_3src_a1_src2_type(devinfo, inst)) == 1,
"Byte data type is not supported for src1/2 register regioning. This includes "