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radv: allow to disable anisotropic filtering for single level image with drirc

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14471>
This commit is contained in:
Samuel Pitoiset
2021-12-27 14:18:59 +01:00
committed by Marge Bot
parent 874f4095c5
commit e6173ed1d2
8 changed files with 53 additions and 3 deletions
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22
src/amd/compiler/aco_instruction_selection.cpp
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@@ -9124,6 +9124,28 @@ tex_fetch_ptrs(isel_context* ctx, nir_tex_instr* instr, Temp* res_ptr, Temp* sam
}
if (samp_ptr) {
*samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false);
if (ctx->options->disable_aniso_single_level &&
instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
/* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
Builder bld(ctx->program, ctx->block);
/* to avoid unnecessary moves, we split and recombine sampler and image */
Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
Definition(img[2]), Definition(img[3]), Definition(img[4]), Definition(img[5]),
Definition(img[6]), Definition(img[7]), *res_ptr);
bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
Definition(samp[2]), Definition(samp[3]), *samp_ptr);
samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
*res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8), img[0], img[1], img[2],
img[3], img[4], img[5], img[6], img[7]);
*samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), samp[0], samp[1], samp[2],
samp[3]);
}
}
}

13
src/amd/vulkan/radv_device.c
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@@ -916,6 +916,7 @@ static const driOptionDescription radv_dri_options[] = {
DRI_CONF_RADV_REPORT_APU_AS_DGPU(false)
DRI_CONF_RADV_REQUIRE_ETC2(false)
DRI_CONF_RADV_DISABLE_HTILE_LAYERS(false)
DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(false)
DRI_CONF_SECTION_END
};
// clang-format on
@@ -964,6 +965,9 @@ radv_init_dri_options(struct radv_instance *instance)
instance->disable_htile_layers =
driQueryOptionb(&instance->dri_options, "radv_disable_htile_layers");
instance->disable_aniso_single_level =
driQueryOptionb(&instance->dri_options, "radv_disable_aniso_single_level");
}
VKAPI_ATTR VkResult VKAPI_CALL
@@ -6096,10 +6100,15 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler,
sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
if (device->physical_device->rad_info.chip_class < GFX10) {
if (device->physical_device->rad_info.chip_class >= GFX10) {
sampler->state[2] |=
S_008F38_ANISO_OVERRIDE_GFX10(device->instance->disable_aniso_single_level);
} else {
sampler->state[2] |=
S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
S_008F38_FILTER_PREC_FIX(1);
S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE_GFX8(device->instance->disable_aniso_single_level &&
device->physical_device->rad_info.chip_class >= GFX8);
}
}

12
src/amd/vulkan/radv_image.c
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@@ -1183,6 +1183,18 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) &&
image->planes[0].surface.meta_offset) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
} else {
if (device->instance->disable_aniso_single_level) {
/* The last dword is unused by hw. The shader uses it to clear
* bits in the first dword of sampler state.
*/
if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
if (first_level == last_level)
state[7] = C_008F30_MAX_ANISO_RATIO;
else
state[7] = 0xffffffff;
}
}
}
/* Initialize the sampler view for FMASK. */

2
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -2394,7 +2394,7 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ctx.abi.clamp_shadow_reference = false;
ctx.abi.adjust_frag_coord_z = options->adjust_frag_coord_z;
ctx.abi.robust_buffer_access = options->robust_buffer_access;
ctx.abi.disable_aniso_single_level = false;
ctx.abi.disable_aniso_single_level = options->disable_aniso_single_level;
bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && info->is_ngg;
if (shader_count >= 2 || is_ngg)

1
src/amd/vulkan/radv_private.h
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@@ -338,6 +338,7 @@ struct radv_instance {
bool absolute_depth_bias;
bool report_apu_as_dgpu;
bool disable_htile_layers;
bool disable_aniso_single_level;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);

1
src/amd/vulkan/radv_shader.c
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@@ -1853,6 +1853,7 @@ shader_compile(struct radv_device *device, struct vk_shader_module *module,
options->enable_mrt_output_nan_fixup =
module && !is_meta_shader(module->nir) && options->key.ps.enable_mrt_output_nan_fixup;
options->adjust_frag_coord_z = device->adjust_frag_coord_z;
options->disable_aniso_single_level = device->instance->disable_aniso_single_level;
options->has_image_load_dcc_bug = device->physical_device->rad_info.has_image_load_dcc_bug;
options->debug.func = radv_compiler_debug;
options->debug.private_data = &debug_data;

1
src/amd/vulkan/radv_shader.h
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@@ -122,6 +122,7 @@ struct radv_nir_compiler_options {
bool enable_mrt_output_nan_fixup;
bool wgp_mode;
bool remap_spi_ps_input;
bool disable_aniso_single_level;
enum radeon_family family;
enum chip_class chip_class;
const struct radeon_info *info;

4
src/util/driconf.h
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@@ -568,4 +568,8 @@
DRI_CONF_OPT_B(radv_disable_htile_layers, def, \
"Disable HTILE for layered depth/stencil formats")
#define DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(def) \
DRI_CONF_OPT_B(radv_disable_aniso_single_level, def, \
"Disable anisotropic filtering for single level images")
#endif