From e50bae00f480d3061f096d6840ec6528a0fd66cb Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sat, 17 Apr 2021 09:58:20 -0400 Subject: [PATCH] agx: Add 32-bit bitwise shifts Only ishr has an actual native instruction, the others are special cases of the bitfield insertion/extraction ops. Signed-off-by: Alyssa Rosenzweig Acked-by: Jason Ekstrand Acked-by: Bas Nieuwenhuizen Part-of: --- src/asahi/compiler/agx_compile.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index d9215c80e61..7def357336c 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -263,6 +263,10 @@ agx_emit_alu(agx_builder *b, nir_alu_instr *instr) case nir_op_ineg: return agx_iadd_to(b, dst, agx_zero(), agx_neg(s0), 0); case nir_op_imul: return agx_imad_to(b, dst, s0, s1, agx_zero(), 0); + case nir_op_ishl: return agx_bfi_to(b, dst, s0, agx_zero(), s1, 0); + case nir_op_ushr: return agx_bfeil_to(b, dst, agx_zero(), s0, s1, 0); + case nir_op_ishr: return agx_asr_to(b, dst, s0, s1); + case nir_op_iadd_sat: { agx_instr *I = agx_iadd_to(b, dst, s0, s1, 0);