From e48c0fbd8f70df5f74bdbe594f807d09fc3a4424 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 24 Aug 2022 15:35:57 +0200 Subject: [PATCH] radv: add support for dynamic depth clamp enable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 66 ++++++++++++++++++++++++++++---- src/amd/vulkan/radv_pipeline.c | 39 +++---------------- src/amd/vulkan/radv_private.h | 3 +- 3 files changed, 65 insertions(+), 43 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 87c4eea0db7..eb64086efd2 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -132,6 +132,7 @@ const struct radv_dynamic_state default_dynamic_state = { .conservative_rast_mode = VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT, .depth_clip_negative_one_to_one = 0u, .provoking_vertex_mode = VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT, + .depth_clamp_enable = 0u, }; static void @@ -285,6 +286,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy RADV_CMP_COPY(provoking_vertex_mode, RADV_DYNAMIC_PROVOKING_VERTEX_MODE); + RADV_CMP_COPY(depth_clamp_enable, RADV_DYNAMIC_DEPTH_CLAMP_ENABLE); + #undef RADV_CMP_COPY cmd_buffer->state.dirty |= dest_mask; @@ -1487,11 +1490,9 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE | RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | RADV_CMD_DIRTY_DYNAMIC_POLYGON_MODE | - RADV_CMD_DIRTY_DYNAMIC_PROVOKING_VERTEX_MODE; - - if (!cmd_buffer->state.emitted_graphics_pipeline || - cmd_buffer->state.emitted_graphics_pipeline->depth_clamp_mode != pipeline->depth_clamp_mode) - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT; + RADV_CMD_DIRTY_DYNAMIC_PROVOKING_VERTEX_MODE | + RADV_CMD_DIRTY_DYNAMIC_VIEWPORT | + RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE; if (!cmd_buffer->state.emitted_graphics_pipeline || radv_rast_prim_is_points_or_lines(cmd_buffer->state.emitted_graphics_pipeline->rast_prim) != radv_rast_prim_is_points_or_lines(pipeline->rast_prim)) @@ -1584,12 +1585,34 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE; } +static enum radv_depth_clamp_mode +radv_get_depth_clamp_mode(struct radv_cmd_buffer *cmd_buffer) +{ + const struct radv_device *device = cmd_buffer->device; + struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + enum radv_depth_clamp_mode mode; + + mode = RADV_DEPTH_CLAMP_MODE_VIEWPORT; + if (!d->depth_clamp_enable) { + /* For optimal performance, depth clamping should always be enabled except if the application + * disables clamping explicitly or uses depth values outside of the [0.0, 1.0] range. + */ + if (!d->depth_clip_enable || device->vk.enabled_extensions.EXT_depth_range_unrestricted) { + mode = RADV_DEPTH_CLAMP_MODE_DISABLED; + } else { + mode = RADV_DEPTH_CLAMP_MODE_ZERO_TO_ONE; + } + } + + return mode; +} + static void radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer) { - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; const struct radv_viewport_state *viewport = &cmd_buffer->state.dynamic.viewport; + enum radv_depth_clamp_mode depth_clamp_mode = radv_get_depth_clamp_mode(cmd_buffer); int i; const unsigned count = viewport->count; @@ -1619,7 +1642,7 @@ radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer) for (i = 0; i < count; i++) { float zmin, zmax; - if (pipeline->depth_clamp_mode == RADV_DEPTH_CLAMP_MODE_ZERO_TO_ONE) { + if (depth_clamp_mode == RADV_DEPTH_CLAMP_MODE_ZERO_TO_ONE) { zmin = 0.0f; zmax = 1.0f; } else { @@ -2039,6 +2062,17 @@ radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer) radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, db_eqaa); } +static void +radv_emit_depth_clamp_enable(struct radv_cmd_buffer *cmd_buffer) +{ + enum radv_depth_clamp_mode mode = radv_get_depth_clamp_mode(cmd_buffer); + + radeon_set_context_reg(cmd_buffer->cs, R_02800C_DB_RENDER_OVERRIDE, + S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | + S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) | + S_02800C_DISABLE_VIEWPORT_CLAMP(mode == RADV_DEPTH_CLAMP_MODE_DISABLED)); +} + static void radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct radv_color_buffer_info *cb, struct radv_image_view *iview, @@ -3463,7 +3497,9 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip cmd_buffer->state.dirty & cmd_buffer->state.emitted_graphics_pipeline->needed_dynamic_state; if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT | - RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE)) + RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE | + RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE)) radv_emit_viewport(cmd_buffer); if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) && @@ -3551,6 +3587,9 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_MASK) radv_emit_sample_mask(cmd_buffer); + if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE) + radv_emit_depth_clamp_enable(cmd_buffer); + cmd_buffer->state.dirty &= ~states; } @@ -6058,6 +6097,17 @@ radv_CmdSetProvokingVertexModeEXT(VkCommandBuffer commandBuffer, state->dirty |= RADV_CMD_DIRTY_DYNAMIC_PROVOKING_VERTEX_MODE; } +VKAPI_ATTR void VKAPI_CALL +radv_CmdSetDepthClampEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthClampEnable) +{ + RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); + struct radv_cmd_state *state = &cmd_buffer->state; + + state->dynamic.depth_clamp_enable = depthClampEnable; + + state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE; +} + VKAPI_ATTR void VKAPI_CALL radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer *pCmdBuffers) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 40d68efb198..9e34cb218d9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -71,7 +71,6 @@ struct radv_blend_state { struct radv_depth_stencil_state { uint32_t db_render_control; - uint32_t db_render_override; uint32_t db_render_override2; }; @@ -1901,29 +1900,11 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline, dynamic->provoking_vertex_mode = state->rs->provoking_vertex; } - pipeline->dynamic_state.mask = states; -} - -static void -radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline, - const struct vk_graphics_pipeline_state *state) -{ - const struct radv_device *device = pipeline->base.device; - - pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_VIEWPORT; - if (!state->rs->depth_clamp_enable) { - /* For optimal performance, depth clamping should always be enabled except if the - * application disables clamping explicitly or uses depth values outside of the [0.0, 1.0] - * range. - */ - if ((!state->rs->depth_clip_enable && - !(pipeline->dynamic_states & RADV_DYNAMIC_DEPTH_CLIP_ENABLE)) || - device->vk.enabled_extensions.EXT_depth_range_unrestricted) { - pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_DISABLED; - } else { - pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_ZERO_TO_ONE; - } + if (states & RADV_DYNAMIC_DEPTH_CLAMP_ENABLE) { + dynamic->depth_clamp_enable = state->rs->depth_clamp_enable; } + + pipeline->dynamic_state.mask = states; } static struct radv_depth_stencil_state @@ -1944,12 +1925,6 @@ radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline, ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1); } - ds_state.db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | - S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); - - if (pipeline->depth_clamp_mode == RADV_DEPTH_CLAMP_MODE_DISABLED) - ds_state.db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1); - if (pdevice->rad_info.gfx_level >= GFX11) { unsigned max_allowed_tiles_in_wave = 0; unsigned num_samples = MAX2(radv_pipeline_color_samples(state), @@ -4764,9 +4739,7 @@ radv_pipeline_emit_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, { radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, ds_state->db_render_control); - radeon_set_context_reg_seq(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, 2); - radeon_emit(ctx_cs, ds_state->db_render_override); - radeon_emit(ctx_cs, ds_state->db_render_override2); + radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, ds_state->db_render_override2); } static void @@ -6163,8 +6136,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv radv_pipeline_init_input_assembly_state(pipeline); radv_pipeline_init_dynamic_state(pipeline, &state); - radv_pipeline_init_raster_state(pipeline, &state); - struct radv_depth_stencil_state ds_state = radv_pipeline_init_depth_stencil_state(pipeline, &state); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 7d27f377537..f3673d6289e 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1371,6 +1371,8 @@ struct radv_dynamic_state { bool depth_clip_negative_one_to_one; VkProvokingVertexModeEXT provoking_vertex_mode; + + bool depth_clamp_enable; }; extern const struct radv_dynamic_state default_dynamic_state; @@ -2073,7 +2075,6 @@ struct radv_graphics_pipeline { bool disable_out_of_order_rast_for_occlusion; bool uses_drawid; bool uses_baseinstance; - enum radv_depth_clamp_mode depth_clamp_mode; bool use_per_attribute_vb_descs; bool can_use_simple_input; bool uses_user_sample_locations;