OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

freedreno/devices: Update magic regs for a7xx

Browse Source 
These regs are written by blob, for some of them blob could
write non-zero values. So executing Turnip after blob without
writing these regs could lead to nasty GPU crashes.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
This commit is contained in:
Danylo Piliaiev
2024-02-07 11:47:50 +01:00
committed by Marge Bot
parent eb1e71e707
commit e4631bee61
3 changed files with 31 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/freedreno/common/freedreno_dev_info.h
View File

@@ -193,7 +193,7 @@ struct fd_dev_info {
struct {
uint32_t reg;
uint32_t value;
} magic_raw[32];
} magic_raw[64];
/* maximum number of descriptor sets */
uint32_t max_sets;

30
src/freedreno/common/freedreno_devices.py
View File

@@ -841,6 +841,16 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4+1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3],
]
add_gpus([
@@ -940,6 +950,16 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4+1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3],
],
))
@@ -996,6 +1016,16 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4+1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3],
[0x930a, 0],
[0x960a, 1],
[A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL, 0],

1
src/freedreno/vulkan/tu_cmd_buffer.cc
View File

@@ -1715,7 +1715,6 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
/* These three have something to do with lrz/depth */
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_810B(0x3));
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8113(0x4));
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));