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radv: Lower input attachments in NIR.

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v2 (Connor)
- Fix warning in release mode using MAYBE_UNUSED

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Daniel Schürmann
2019-04-05 11:01:39 +02:00
committed by Connor Abbott
parent c65e880a65
commit e41e932e57
6 changed files with 10 additions and 36 deletions
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30
src/amd/common/ac_nir_to_llvm.c
View File

@@ -2330,17 +2330,17 @@ static void get_image_coords(struct ac_nir_context *ctx,
LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
int count;
bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
MAYBE_UNUSED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
assert(!add_frag_pos && "Input attachments should be lowered by this point.");
count = image_type_to_components_count(dim, is_array);
if (is_ms && (instr->intrinsic == nir_intrinsic_image_deref_load ||
instr->intrinsic == nir_intrinsic_bindless_image_load)) {
LLVMValueRef fmask_load_address[3];
int chan;
fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
@@ -2348,14 +2348,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
else
fmask_load_address[2] = NULL;
if (add_frag_pos) {
for (chan = 0; chan < 2; ++chan)
fmask_load_address[chan] =
LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
ctx->ac.i32, ""), "");
fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
}
sample_index = adjust_sample_index_using_fmask(&ctx->ac,
fmask_load_address[0],
fmask_load_address[1],
@@ -2376,18 +2369,6 @@ static void get_image_coords(struct ac_nir_context *ctx,
for (chan = 0; chan < count; ++chan) {
args->coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
}
if (add_frag_pos) {
for (chan = 0; chan < 2; ++chan) {
args->coords[chan] = LLVMBuildAdd(
ctx->ac.builder, args->coords[chan],
LLVMBuildFPToUI(
ctx->ac.builder, ctx->abi->frag_pos[chan],
ctx->ac.i32, ""), "");
}
args->coords[2] = ac_to_integer(&ctx->ac,
ctx->abi->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
count++;
}
if (gfx9_1d) {
if (is_array) {
@@ -3873,7 +3854,8 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
goto write_result;
}
if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
if ((instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ||
instr->sampler_dim == GLSL_SAMPLER_DIM_MS) &&
instr->op != nir_texop_txs) {
unsigned sample_chan = instr->is_array ? 3 : 2;
args.coords[sample_chan] = adjust_sample_index_using_fmask(

3
src/amd/vulkan/radv_nir_to_llvm.c
View File

@@ -2478,8 +2478,7 @@ handle_fs_inputs(struct radv_shader_context *ctx,
unsigned index = 0;
if (ctx->shader_info->info.ps.uses_input_attachments ||
ctx->shader_info->info.needs_multiview_view_index ||
if (ctx->shader_info->info.needs_multiview_view_index ||
ctx->shader_info->info.ps.layer_input) {
ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);

1
src/amd/vulkan/radv_pipeline.c
View File

@@ -3640,7 +3640,6 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
}
if (ps->info.info.ps.layer_input ||
ps->info.info.ps.uses_input_attachments ||
ps->info.info.needs_multiview_view_index) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
if (vs_offset != AC_EXP_PARAM_UNDEFINED)

3
src/amd/vulkan/radv_shader.c
View File

@@ -334,6 +334,9 @@ radv_shader_compile_to_nir(struct radv_device *device,
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_split_per_member_structs);
if (nir->info.stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, nir_lower_input_attachments);
NIR_PASS_V(nir, nir_remove_dead_variables,
nir_var_shader_in | nir_var_shader_out | nir_var_system_value);

1
src/amd/vulkan/radv_shader.h
View File

@@ -206,7 +206,6 @@ struct radv_shader_info {
struct {
bool force_persample;
bool needs_sample_positions;
bool uses_input_attachments;
bool writes_memory;
bool writes_z;
bool writes_stencil;

8
src/amd/vulkan/radv_shader_info.c
View File

@@ -293,14 +293,6 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
case nir_intrinsic_image_deref_atomic_comp_swap:
case nir_intrinsic_image_deref_size: {
nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
const struct glsl_type *type = glsl_without_array(var->type);
enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
info->ps.layer_input = true;
info->ps.uses_input_attachments = true;
}
mark_sampler_desc(var, info);
if (instr->intrinsic == nir_intrinsic_image_deref_store ||