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radeonsi/gfx12: set DB_RENDER_OVERRIDE based on stencil state

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32653>
This commit is contained in:
Marek Olšák
2024-12-16 03:48:37 -05:00
committed by Marge Bot
parent 8328e57512
commit e3cef02c24
5 changed files with 15 additions and 1 deletions
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1
src/amd/common/ac_cmdbuf.c
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@@ -605,7 +605,6 @@ gfx12_init_graphics_preamble_state(const struct ac_preamble_state *state,
ac_pm4_set_reg(pm4, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0);
/* Context registers */
ac_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, S_02800C_FORCE_STENCIL_READ(1));
ac_pm4_set_reg(pm4, R_028040_DB_GL1_INTERFACE_CONTROL, 0);
ac_pm4_set_reg(pm4, R_028048_DB_MEM_TEMPORAL,
S_028048_Z_TEMPORAL_READ(zs_read_temporal_hint) |

4
src/amd/vulkan/radv_queue.c
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@@ -886,6 +886,10 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, 0);
radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
S_02800C_FORCE_STENCIL_READ(1) |
/* TODO: this should be conditional based on stencil state */
S_02800C_FORCE_STENCIL_VALID(1));
}
ac_pm4_finalize(pm4);

1
src/gallium/drivers/radeonsi/si_gfx_cs.c
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@@ -317,6 +317,7 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0;

8
src/gallium/drivers/radeonsi/si_state.c
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@@ -1553,6 +1553,12 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
S_028090_TESTMASK_BF(state->stencil[1].valuemask);
dsa->db_stencil_write_mask = S_028094_WRITEMASK(state->stencil[0].writemask) |
S_028094_WRITEMASK_BF(state->stencil[1].writemask);
bool force_s_valid = state->stencil[0].zpass_op != state->stencil[0].zfail_op ||
(state->stencil[1].enabled &&
state->stencil[1].zpass_op != state->stencil[1].zfail_op);
dsa->db_render_override = S_02800C_FORCE_STENCIL_READ(1) |
S_02800C_FORCE_STENCIL_VALID(force_s_valid);
}
bool zfunc_is_ordered =
@@ -1588,6 +1594,8 @@ static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index)
if (sctx->gfx_level >= GFX12) {
radeon_begin(&sctx->gfx_cs);
gfx12_begin_context_regs();
gfx12_opt_set_context_reg(R_02800C_DB_RENDER_OVERRIDE, SI_TRACKED_DB_RENDER_OVERRIDE,
state->db_render_override);
gfx12_opt_set_context_reg(R_028070_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
state->db_depth_control);
if (state->stencil_enabled) {

2
src/gallium/drivers/radeonsi/si_state.h
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@@ -131,6 +131,7 @@ struct si_state_dsa {
unsigned spi_shader_user_data_ps_alpha_ref;
unsigned db_stencil_read_mask;
unsigned db_stencil_write_mask;
unsigned db_render_override; /* only gfx12 */
/* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
struct si_dsa_order_invariance order_invariance[2];
@@ -315,6 +316,7 @@ enum si_tracked_reg
SI_TRACKED_SPI_PS_INPUT_ENA,
SI_TRACKED_SPI_PS_INPUT_ADDR,
SI_TRACKED_DB_RENDER_OVERRIDE,
SI_TRACKED_DB_EQAA,
SI_TRACKED_DB_RENDER_OVERRIDE2,
SI_TRACKED_DB_SHADER_CONTROL,