OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel: Limit Wa_1607854226 to Gfx12.0 only

Browse Source 
This workaround is needed on all Gfx12.0 parts, but doesn't appear to be
necessary on XeHP.  The other drivers do not appear to be applying this
workaround on those parts.  As further evidence, we accidentally added
the 3DSTATE_BINDING_TABLE_POOL_ALLOC commands after switching back to
GPGPU mode, which would be an incorrect way to implement the workaround,
and things seem to be working.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14507>
This commit is contained in:
Kenneth Graunke
2022-01-11 15:06:06 -08:00
committed by Marge Bot
parent ab47cad4fb
commit e3a0e97300
2 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/gallium/drivers/iris/iris_state.c
View File

@@ -1157,7 +1157,7 @@ iris_init_compute_context(struct iris_batch *batch)
* *
* Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS. * Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
*/ */
#if GFX_VER == 12 #if GFX_VERx10 == 120
emit_pipeline_select(batch, _3D); emit_pipeline_select(batch, _3D);
#else #else
emit_pipeline_select(batch, GPGPU); emit_pipeline_select(batch, GPGPU);
@@ -1169,7 +1169,7 @@ iris_init_compute_context(struct iris_batch *batch)
iris_init_common_context(batch); iris_init_common_context(batch);
#if GFX_VER == 12 #if GFX_VERx10 == 120
emit_pipeline_select(batch, GPGPU); emit_pipeline_select(batch, GPGPU);
#endif #endif
@@ -5460,7 +5460,7 @@ iris_update_binder_address(struct iris_batch *batch,
flush_before_state_base_change(batch); flush_before_state_base_change(batch);
#if GFX_VER == 12 #if GFX_VERx10 == 120
/* Wa_1607854226: /* Wa_1607854226:
* *
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
@@ -5491,7 +5491,7 @@ iris_update_binder_address(struct iris_batch *batch,
#endif #endif
} }
#if GFX_VER == 12 #if GFX_VERx10 == 120
/* Wa_1607854226: /* Wa_1607854226:
* *
* Put the pipeline back into compute mode. * Put the pipeline back into compute mode.

4
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -120,7 +120,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
anv_debug_dump_pc(pc); anv_debug_dump_pc(pc);
} }
#if GFX_VER == 12 #if GFX_VERx10 == 120
/* Wa_1607854226: /* Wa_1607854226:
* *
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
@@ -210,7 +210,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
# endif # endif
} }
#if GFX_VER == 12 #if GFX_VERx10 == 120
/* Wa_1607854226: /* Wa_1607854226:
* *
* Put the pipeline back into its current mode. * Put the pipeline back into its current mode.