diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 39b2e657fe8..75f3a466113 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -501,7 +501,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->max_memory_clock = amdinfo->max_memory_clk / 1000; info->num_tcc_blocks = device_info.num_tcc_blocks; info->max_se = amdinfo->num_shader_engines; - info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine; + info->max_sa_per_se = amdinfo->num_shader_arrays_per_engine; info->has_hw_decode = (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) || (vcn_jpeg.available_rings != 0); info->uvd_fw_version = uvd.available_rings ? uvd_version : 0; @@ -657,7 +657,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) { - for (j = 0; j < info->max_sh_per_se; j++) { + for (j = 0; j < info->max_sa_per_se; j++) { /* * The cu bitmap in amd gpu info structure is * 4x4 size array, and it's usually suitable for Vega @@ -680,10 +680,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, */ unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1; info->max_good_cu_per_sa = - DIV_ROUND_UP(info->num_good_compute_units, (info->num_se * info->max_sh_per_se * cu_group)) * + DIV_ROUND_UP(info->num_good_compute_units, (info->num_se * info->max_sa_per_se * cu_group)) * cu_group; info->min_good_cu_per_sa = - (info->num_good_compute_units / (info->num_se * info->max_sh_per_se * cu_group)) * cu_group; + (info->num_good_compute_units / (info->num_se * info->max_sa_per_se * cu_group)) * cu_group; memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, sizeof(amdinfo->gb_tile_mode)); info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask; @@ -973,7 +973,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa); fprintf(f, " max_se = %i\n", info->max_se); fprintf(f, " num_se = %i\n", info->num_se); - fprintf(f, " max_sh_per_se = %i\n", info->max_sh_per_se); + fprintf(f, " max_sa_per_se = %i\n", info->max_sa_per_se); fprintf(f, " max_wave64_per_simd = %i\n", info->max_wave64_per_simd); fprintf(f, " num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd); fprintf(f, " num_physical_wave64_vgprs_per_simd = %i\n", @@ -1165,7 +1165,7 @@ void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, unsigned *cik_raster_config_1_p, unsigned *raster_config_se) { - unsigned sh_per_se = MAX2(info->max_sh_per_se, 1); + unsigned sh_per_se = MAX2(info->max_sa_per_se, 1); unsigned num_se = MAX2(info->max_se, 1); unsigned rb_mask = info->enabled_rb_mask; unsigned num_rb = MIN2(info->max_render_backends, 16); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 893220d25cc..40b6f1b6bdb 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -168,7 +168,7 @@ struct radeon_info { uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */ uint32_t max_se; /* number of shader engines incl. disabled ones */ uint32_t num_se; /* number of enabled shader engines */ - uint32_t max_sh_per_se; /* shader arrays per shader engine */ + uint32_t max_sa_per_se; /* shader arrays per shader engine */ uint32_t max_wave64_per_simd; uint32_t num_physical_sgprs_per_simd; uint32_t num_physical_wave64_vgprs_per_simd; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index ebe85e28207..56d4e472bb5 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1879,7 +1879,7 @@ void radv_GetPhysicalDeviceProperties2( properties->shaderEngineCount = pdevice->rad_info.max_se; properties->shaderArraysPerEngineCount = - pdevice->rad_info.max_sh_per_se; + pdevice->rad_info.max_sa_per_se; properties->computeUnitsPerShaderArray = pdevice->rad_info.min_good_cu_per_sa; properties->simdPerComputeUnit = diff --git a/src/amd/vulkan/radv_rgp.c b/src/amd/vulkan/radv_rgp.c index d9f41587fad..efcf2ae0fe4 100644 --- a/src/amd/vulkan/radv_rgp.c +++ b/src/amd/vulkan/radv_rgp.c @@ -361,7 +361,7 @@ radv_fill_sqtt_asic_info(struct radv_device *device, chunk->sgprs_per_simd = rad_info->num_physical_sgprs_per_simd; chunk->shader_engines = rad_info->max_se; chunk->compute_unit_per_shader_engine = rad_info->min_good_cu_per_sa * - rad_info->max_sh_per_se; + rad_info->max_sa_per_se; chunk->simd_per_compute_unit = rad_info->num_simd_per_compute_unit; chunk->wavefronts_per_simd = rad_info->max_wave64_per_simd; diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index 309b1ce1da0..5c8e5d52476 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -1344,7 +1344,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock); printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units); printf("max_se = %i\n", rscreen->info.max_se); - printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se); + printf("max_sh_per_se = %i\n", rscreen->info.max_sa_per_se); printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map); printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 700345dd77e..ee62a4077e1 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -531,11 +531,11 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) } radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL, - &ws->info.max_sh_per_se); + &ws->info.max_sa_per_se); if (ws->gen == DRV_SI) { ws->info.max_good_cu_per_sa = ws->info.min_good_cu_per_sa = ws->info.num_good_compute_units / - (ws->info.max_se * ws->info.max_sh_per_se); + (ws->info.max_se * ws->info.max_sa_per_se); } radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,