intel/compiler: Create struct for TCS thread payload

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>

src/intel/compiler/brw_fs.cpp

@@ -6623,27 +6623,13 @@ bool
 fs_visitor::run_tcs()
 {
    assert(stage == MESA_SHADER_TESS_CTRL);
-   thread_payload &payload = this->payload();
 
    struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
-   struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
-   struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
 
    assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH ||
           vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
 
-   if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
+   payload_ = new tcs_thread_payload(*this);
-      /* r1-r4 contain the ICP handles. */
-      payload.num_regs = 5;
-   } else {
-      assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
-      assert(tcs_key->input_vertices > 0);
-      /* r1 contains output handles, r2 may contain primitive ID, then the
-       * ICP handles occupy the next 1-32 registers.
-       */
-      payload.num_regs = 2 + tcs_prog_data->include_primitive_id +
-                         tcs_key->input_vertices;
-   }
 
    /* Initialize gl_InvocationID */
    set_tcs_invocation_id();

src/intel/compiler/brw_fs.h

@@ -93,6 +93,10 @@ struct thread_payload {
    virtual ~thread_payload() = default;
 };
 
+struct tcs_thread_payload : public thread_payload {
+   tcs_thread_payload(const fs_visitor &v);
+};
+
 struct fs_thread_payload : public thread_payload {
    fs_thread_payload(const fs_visitor &v,
                      bool &source_depth_to_render_target,
@@ -421,6 +425,11 @@ public:
       return *this->payload_;
    }
 
+   tcs_thread_payload &tcs_payload() {
+      assert(stage == MESA_SHADER_TESS_CTRL);
+      return *static_cast<tcs_thread_payload *>(this->payload_);
+   }
+
    fs_thread_payload &fs_payload() {
       assert(stage == MESA_SHADER_FRAGMENT);
       return *static_cast<fs_thread_payload *>(this->payload_);

src/intel/compiler/brw_fs_thread_payload.cpp

@@ -25,6 +25,26 @@
 
 using namespace brw;
 
+tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
+{
+   struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data);
+   struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(v.prog_data);
+   struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) v.key;
+
+   if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
+      /* r1-r4 contain the ICP handles. */
+      num_regs = 5;
+   } else {
+      assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
+      assert(tcs_key->input_vertices > 0);
+      /* r1 contains output handles, r2 may contain primitive ID, then the
+       * ICP handles occupy the next 1-32 registers.
+       */
+      num_regs = 2 + tcs_prog_data->include_primitive_id +
+                 tcs_key->input_vertices;
+   }
+}
+
 static inline void
 setup_fs_payload_gfx6(fs_thread_payload &payload,
                       const fs_visitor &v,