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radv/gfx10: fix NGG streamout with triangle strips for VS

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The number of vertices has to be adjusted with the output primitive
type.

This fixes dEQP-VK.transform_feedback.simple.triangle_strip_*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2019-09-17 18:52:02 +02:00
parent 08ab13d340
commit e19d1ee2d1
4 changed files with 13 additions and 1 deletions
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6
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -3702,7 +3702,11 @@ handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
LLVMValueRef num_vertices_val; LLVMValueRef num_vertices_val;
if (ctx->stage == MESA_SHADER_VERTEX) { if (ctx->stage == MESA_SHADER_VERTEX) {
num_vertices_val = LLVMConstInt(ctx->ac.i32, 1, false); LLVMValueRef outprim_val =
LLVMConstInt(ctx->ac.i32,
ctx->options->key.vs.outprim, false);
num_vertices_val = LLVMBuildAdd(builder, outprim_val,
ctx->ac.i32_1, "");
num_vertices = 3; /* TODO: optimize for points & lines */ num_vertices = 3; /* TODO: optimize for points & lines */
} else { } else {
assert(ctx->stage == MESA_SHADER_TESS_EVAL); assert(ctx->stage == MESA_SHADER_TESS_EVAL);

4
src/amd/vulkan/radv_pipeline.c
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@@ -2263,6 +2263,9 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
if (pipeline->device->physical_device->rad_info.chip_class < GFX8) if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10); radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
key.topology = pCreateInfo->pInputAssemblyState->topology;
return key; return key;
} }
@@ -2292,6 +2295,7 @@ radv_fill_shader_keys(struct radv_device *device,
keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i]; keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i]; keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
} }
keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
if (nir[MESA_SHADER_TESS_CTRL]) { if (nir[MESA_SHADER_TESS_CTRL]) {
keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true; keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;

1
src/amd/vulkan/radv_private.h
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@@ -378,6 +378,7 @@ struct radv_pipeline_key {
uint8_t num_samples; uint8_t num_samples;
uint32_t has_multiview_view_index : 1; uint32_t has_multiview_view_index : 1;
uint32_t optimisations_disabled : 1; uint32_t optimisations_disabled : 1;
uint8_t topology;
}; };
struct radv_shader_binary; struct radv_shader_binary;

3
src/amd/vulkan/radv_shader.h
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@@ -76,6 +76,9 @@ struct radv_vs_variant_key {
/* For some formats the channels have to be shuffled. */ /* For some formats the channels have to be shuffled. */
uint32_t post_shuffle; uint32_t post_shuffle;
/* Output primitive type. */
uint8_t outprim;
}; };
struct radv_tes_variant_key { struct radv_tes_variant_key {