OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965/gen8: Factor out texture surface state set-up from gen8_update_texture_surface().

Browse Source 
This moves most of the surface state set-up logic that can be shared
between textures and shader images to a separate function.
This commit is contained in:
Francisco Jerez
2015-04-13 21:38:06 +03:00
parent 6f26ffaf66
commit e17dc004fd
1 changed files with 77 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

135
src/mesa/drivers/dri/i965/gen8_surface_state.c
View File

@@ -150,34 +150,23 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
}
static void
gen8_update_texture_surface(struct gl_context *ctx,
unsigned unit,
gen8_emit_texture_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLenum target,
unsigned min_layer, unsigned max_layer,
unsigned min_level, unsigned max_level,
unsigned format,
unsigned swizzle,
uint32_t *surf_offset,
bool for_gather)
bool rw, bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
const unsigned depth = max_layer - min_layer;
struct intel_mipmap_tree *aux_mt = NULL;
uint32_t aux_mode = 0;
mesa_format format = intelObj->_Format;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
if (tObj->Target == GL_TEXTURE_BUFFER) {
brw_update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
mt = mt->stencil_mt;
format = MESA_FORMAT_S_UINT8;
}
unsigned tiling_mode, pitch;
if (format == MESA_FORMAT_S_UINT8) {
if (mt->format == MESA_FORMAT_S_UINT8) {
tiling_mode = GEN8_SURFACE_TILING_W;
pitch = 2 * mt->pitch;
} else {
@@ -190,30 +179,20 @@ gen8_update_texture_surface(struct gl_context *ctx,
aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
}
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
uint32_t effective_depth =
(tObj->Immutable && tObj->Target != GL_TEXTURE_3D) ? tObj->NumLayers
: mt->logical_depth0;
uint32_t tex_format = translate_tex_format(brw, format, sampler->sRGBDecode);
uint32_t *surf = allocate_surface_state(brw, surf_offset);
surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
tex_format << BRW_SURFACE_FORMAT_SHIFT |
surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT |
vertical_alignment(mt) |
horizontal_alignment(mt) |
tiling_mode;
if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
if (target == GL_TEXTURE_CUBE_MAP ||
target == GL_TEXTURE_CUBE_MAP_ARRAY) {
surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
}
if (_mesa_is_array_texture(tObj->Target) ||
tObj->Target == GL_TEXTURE_CUBE_MAP)
if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
surf[0] |= GEN8_SURFACE_IS_ARRAY;
surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
@@ -221,16 +200,14 @@ gen8_update_texture_surface(struct gl_context *ctx,
surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
SET_FIELD(effective_depth - 1,
GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
surf[5] = SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level,
GEN7_SURFACE_MIN_LOD) |
(intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
(max_level - min_level - 1); /* mip count */
if (aux_mt) {
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
@@ -240,19 +217,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
surf[6] = 0;
}
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
* texturing functions that return a float, as our code generation always
* selects the .x channel (which would always be 0).
*/
const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
(firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
firstImage->_BaseFormat == GL_DEPTH_STENCIL);
surf[7] = mt->fast_clear_color_value;
const int swizzle =
unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
surf[7] |=
surf[7] = mt->fast_clear_color_value |
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
@@ -264,7 +229,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
*((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
aux_mt->bo, 0,
I915_GEM_DOMAIN_SAMPLER, 0);
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
} else {
surf[10] = 0;
surf[11] = 0;
@@ -276,7 +242,57 @@ gen8_update_texture_surface(struct gl_context *ctx,
*surf_offset + 8 * 4,
mt->bo,
mt->offset,
I915_GEM_DOMAIN_SAMPLER, 0);
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
}
static void
gen8_update_texture_surface(struct gl_context *ctx,
unsigned unit,
uint32_t *surf_offset,
bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
if (obj->Target == GL_TEXTURE_BUFFER) {
brw_update_buffer_texture_surface(ctx, unit, surf_offset);
} else {
struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
struct intel_texture_object *intel_obj = intel_texture_object(obj);
struct intel_mipmap_tree *mt = intel_obj->mt;
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
obj->NumLayers : mt->logical_depth0);
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
* texturing functions that return a float, as our code generation always
* selects the .x channel (which would always be 0).
*/
const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
(firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
firstImage->_BaseFormat == GL_DEPTH_STENCIL);
const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
brw_get_texture_swizzle(&brw->ctx, obj));
unsigned format = translate_tex_format(brw, intel_obj->_Format,
sampler->sRGBDecode);
if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
mt = mt->stencil_mt;
format = BRW_SURFACEFORMAT_R8_UINT;
}
gen8_emit_texture_surface_state(brw, mt, obj->Target,
obj->MinLayer, obj->MinLayer + depth,
obj->MinLevel + obj->BaseLevel,
obj->MinLevel + intel_obj->_MaxLevel + 1,
format, swizzle, surf_offset,
false, for_gather);
}
}
/**
@@ -446,5 +462,6 @@ gen8_init_vtable_surface_functions(struct brw_context *brw)
brw->vtbl.update_texture_surface = gen8_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
}