i965/gen8: Factor out texture surface state set-up from gen8_update_texture_surface().
This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
This commit is contained in:
@@ -150,34 +150,23 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
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static void
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static void
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gen8_update_texture_surface(struct gl_context *ctx,
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gen8_emit_texture_surface_state(struct brw_context *brw,
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unsigned unit,
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struct intel_mipmap_tree *mt,
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uint32_t *surf_offset,
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GLenum target,
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bool for_gather)
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unsigned min_layer, unsigned max_layer,
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unsigned min_level, unsigned max_level,
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unsigned format,
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unsigned swizzle,
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uint32_t *surf_offset,
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bool rw, bool for_gather)
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{
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{
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struct brw_context *brw = brw_context(ctx);
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const unsigned depth = max_layer - min_layer;
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struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
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struct intel_texture_object *intelObj = intel_texture_object(tObj);
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struct intel_mipmap_tree *mt = intelObj->mt;
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struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
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struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
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struct intel_mipmap_tree *aux_mt = NULL;
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struct intel_mipmap_tree *aux_mt = NULL;
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uint32_t aux_mode = 0;
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uint32_t aux_mode = 0;
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mesa_format format = intelObj->_Format;
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uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
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uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
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if (tObj->Target == GL_TEXTURE_BUFFER) {
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brw_update_buffer_texture_surface(ctx, unit, surf_offset);
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return;
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}
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if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
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mt = mt->stencil_mt;
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format = MESA_FORMAT_S_UINT8;
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}
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unsigned tiling_mode, pitch;
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unsigned tiling_mode, pitch;
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if (format == MESA_FORMAT_S_UINT8) {
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if (mt->format == MESA_FORMAT_S_UINT8) {
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tiling_mode = GEN8_SURFACE_TILING_W;
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tiling_mode = GEN8_SURFACE_TILING_W;
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pitch = 2 * mt->pitch;
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pitch = 2 * mt->pitch;
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} else {
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} else {
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@@ -190,30 +179,20 @@ gen8_update_texture_surface(struct gl_context *ctx,
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aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
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aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
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}
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}
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/* If this is a view with restricted NumLayers, then our effective depth
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* is not just the miptree depth.
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*/
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uint32_t effective_depth =
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(tObj->Immutable && tObj->Target != GL_TEXTURE_3D) ? tObj->NumLayers
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: mt->logical_depth0;
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uint32_t tex_format = translate_tex_format(brw, format, sampler->sRGBDecode);
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uint32_t *surf = allocate_surface_state(brw, surf_offset);
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uint32_t *surf = allocate_surface_state(brw, surf_offset);
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surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
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surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
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tex_format << BRW_SURFACE_FORMAT_SHIFT |
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format << BRW_SURFACE_FORMAT_SHIFT |
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vertical_alignment(mt) |
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vertical_alignment(mt) |
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horizontal_alignment(mt) |
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horizontal_alignment(mt) |
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tiling_mode;
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tiling_mode;
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if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
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if (target == GL_TEXTURE_CUBE_MAP ||
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tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
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target == GL_TEXTURE_CUBE_MAP_ARRAY) {
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surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
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surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
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}
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}
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if (_mesa_is_array_texture(tObj->Target) ||
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if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
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tObj->Target == GL_TEXTURE_CUBE_MAP)
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surf[0] |= GEN8_SURFACE_IS_ARRAY;
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surf[0] |= GEN8_SURFACE_IS_ARRAY;
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surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
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surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
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@@ -221,16 +200,14 @@ gen8_update_texture_surface(struct gl_context *ctx,
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surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
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surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
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SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
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SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
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surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
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surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
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surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
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surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
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SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
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SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
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SET_FIELD(effective_depth - 1,
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SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
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GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
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surf[5] = SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level,
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surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
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GEN7_SURFACE_MIN_LOD) |
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(max_level - min_level - 1); /* mip count */
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(intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
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if (aux_mt) {
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if (aux_mt) {
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surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
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surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
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@@ -240,19 +217,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
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surf[6] = 0;
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surf[6] = 0;
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}
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}
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/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
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surf[7] = mt->fast_clear_color_value |
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* texturing functions that return a float, as our code generation always
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* selects the .x channel (which would always be 0).
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*/
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const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
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(firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
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firstImage->_BaseFormat == GL_DEPTH_STENCIL);
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surf[7] = mt->fast_clear_color_value;
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const int swizzle =
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unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
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surf[7] |=
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
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SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
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@@ -264,7 +229,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
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*((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
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*((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
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drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
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drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
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aux_mt->bo, 0,
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aux_mt->bo, 0,
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I915_GEM_DOMAIN_SAMPLER, 0);
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I915_GEM_DOMAIN_SAMPLER,
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(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
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} else {
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} else {
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surf[10] = 0;
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surf[10] = 0;
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surf[11] = 0;
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surf[11] = 0;
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@@ -276,7 +242,57 @@ gen8_update_texture_surface(struct gl_context *ctx,
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*surf_offset + 8 * 4,
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*surf_offset + 8 * 4,
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mt->bo,
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mt->bo,
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mt->offset,
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mt->offset,
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I915_GEM_DOMAIN_SAMPLER, 0);
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I915_GEM_DOMAIN_SAMPLER,
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(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
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}
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static void
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gen8_update_texture_surface(struct gl_context *ctx,
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unsigned unit,
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uint32_t *surf_offset,
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bool for_gather)
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{
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struct brw_context *brw = brw_context(ctx);
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struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
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if (obj->Target == GL_TEXTURE_BUFFER) {
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brw_update_buffer_texture_surface(ctx, unit, surf_offset);
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} else {
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struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
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struct intel_texture_object *intel_obj = intel_texture_object(obj);
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struct intel_mipmap_tree *mt = intel_obj->mt;
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struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
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/* If this is a view with restricted NumLayers, then our effective depth
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* is not just the miptree depth.
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*/
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const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
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obj->NumLayers : mt->logical_depth0);
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/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
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* texturing functions that return a float, as our code generation always
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* selects the .x channel (which would always be 0).
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*/
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const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
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(firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
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firstImage->_BaseFormat == GL_DEPTH_STENCIL);
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const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
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brw_get_texture_swizzle(&brw->ctx, obj));
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unsigned format = translate_tex_format(brw, intel_obj->_Format,
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sampler->sRGBDecode);
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if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
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mt = mt->stencil_mt;
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format = BRW_SURFACEFORMAT_R8_UINT;
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}
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gen8_emit_texture_surface_state(brw, mt, obj->Target,
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obj->MinLayer, obj->MinLayer + depth,
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obj->MinLevel + obj->BaseLevel,
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obj->MinLevel + intel_obj->_MaxLevel + 1,
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format, swizzle, surf_offset,
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false, for_gather);
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}
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}
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}
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/**
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/**
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@@ -446,5 +462,6 @@ gen8_init_vtable_surface_functions(struct brw_context *brw)
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brw->vtbl.update_texture_surface = gen8_update_texture_surface;
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brw->vtbl.update_texture_surface = gen8_update_texture_surface;
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brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
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brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
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brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
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brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
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brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
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brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
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brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
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}
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}
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