diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index fa3e329a5ab..773846dd2e1 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -11516,7 +11516,7 @@ create_fs_exports(isel_context* ctx)
          out.is_int8 = (ctx->options->key.ps.epilog.color_is_int8 >> idx) & 1;
          out.is_int10 = (ctx->options->key.ps.epilog.color_is_int10 >> idx) & 1;
          out.enable_mrt_output_nan_fixup =
-            (ctx->options->key.ps.epilog.enable_mrt_output_nan_fixup >> idx) & 1;
+            (ctx->options->enable_mrt_output_nan_fixup >> idx) & 1;
 
          for (unsigned c = 0; c < 4; ++c) {
             if (out.write_mask & (1 << c)) {
diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h
index cec8fd7c015..e292262261d 100644
--- a/src/amd/compiler/aco_shader_info.h
+++ b/src/amd/compiler/aco_shader_info.h
@@ -171,6 +171,7 @@ struct aco_compiler_options {
    bool record_ir;
    bool record_stats;
    bool has_ls_vgpr_init_bug;
+   uint8_t enable_mrt_output_nan_fixup;
    bool wgp_mode;
    enum radeon_family family;
    enum amd_gfx_level gfx_level;
diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h
index e090595557e..8394b5ec71f 100644
--- a/src/amd/vulkan/radv_aco_shader_info.h
+++ b/src/amd/vulkan/radv_aco_shader_info.h
@@ -149,6 +149,7 @@ radv_aco_convert_opts(struct aco_compiler_options *aco_info,
    ASSIGN_FIELD(record_ir);
    ASSIGN_FIELD(record_stats);
    ASSIGN_FIELD(has_ls_vgpr_init_bug);
+   ASSIGN_FIELD(enable_mrt_output_nan_fixup);
    ASSIGN_FIELD(wgp_mode);
    ASSIGN_FIELD(family);
    ASSIGN_FIELD(gfx_level);
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 543bc132730..2895da4130e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -567,8 +567,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, LLVMValueRef *values,
          (ctx->options->key.ps.epilog.spi_shader_col_format >> (4 * index)) & 0xf;
       bool is_int8 = (ctx->options->key.ps.epilog.color_is_int8 >> index) & 1;
       bool is_int10 = (ctx->options->key.ps.epilog.color_is_int10 >> index) & 1;
-      bool enable_mrt_output_nan_fixup =
-         (ctx->options->key.ps.epilog.enable_mrt_output_nan_fixup >> index) & 1;
+      bool enable_mrt_output_nan_fixup = (ctx->options->enable_mrt_output_nan_fixup >> index) & 1;
 
       LLVMValueRef (*packf)(struct ac_llvm_context * ctx, LLVMValueRef args[2]) = NULL;
       LLVMValueRef (*packi)(struct ac_llvm_context * ctx, LLVMValueRef args[2], unsigned bits,
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index a392ae8b693..661b4288f87 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -2375,8 +2375,9 @@ radv_fill_nir_compiler_options(struct radv_nir_compiler_options *options,
    options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
    options->address32_hi = device->physical_device->rad_info.address32_hi;
    options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
-   options->enable_mrt_output_nan_fixup =
-      !is_meta_shader && options->key.ps.epilog.enable_mrt_output_nan_fixup;
+
+   if (!is_meta_shader)
+      options->enable_mrt_output_nan_fixup = options->key.ps.epilog.enable_mrt_output_nan_fixup;
 }
 
 static struct radv_shader *