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amd/registers: unify VRS combiner definition names between gfx103 and gfx11

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use gfx11 names

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
This commit is contained in:
Marek Olšák
2023-02-17 18:44:29 -05:00
committed by Marge Bot
parent 091268944d
commit e0c8b24e22
6 changed files with 25 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/amd/registers/gfx103.json
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@@ -909,11 +909,11 @@
}, },
"VRSCombinerModeSC": { "VRSCombinerModeSC": {
"entries": [ "entries": [
{"name": "VRS_COMB_MODE_PASSTHRU", "value": 0}, {"name": "SC_VRS_COMB_MODE_PASSTHRU", "value": 0},
{"name": "VRS_COMB_MODE_OVERRIDE", "value": 1}, {"name": "SC_VRS_COMB_MODE_OVERRIDE", "value": 1},
{"name": "VRS_COMB_MODE_MIN", "value": 2}, {"name": "SC_VRS_COMB_MODE_MIN", "value": 2},
{"name": "VRS_COMB_MODE_MAX", "value": 3}, {"name": "SC_VRS_COMB_MODE_MAX", "value": 3},
{"name": "VRS_COMB_MODE_SATURATE", "value": 4} {"name": "SC_VRS_COMB_MODE_SATURATE", "value": 4}
] ]
}, },
"VRSHtileEncoding": { "VRSHtileEncoding": {

10
src/amd/registers/parse_kernel_headers.py
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@@ -407,11 +407,11 @@ IMG_DATA_FORMAT_STENCIL = {
VRSCombinerModeSC = { VRSCombinerModeSC = {
"entries": [ "entries": [
{"name": "VRS_COMB_MODE_PASSTHRU", "value": 0}, {"name": "SC_VRS_COMB_MODE_PASSTHRU", "value": 0},
{"name": "VRS_COMB_MODE_OVERRIDE", "value": 1}, {"name": "SC_VRS_COMB_MODE_OVERRIDE", "value": 1},
{"name": "VRS_COMB_MODE_MIN", "value": 2}, {"name": "SC_VRS_COMB_MODE_MIN", "value": 2},
{"name": "VRS_COMB_MODE_MAX", "value": 3}, {"name": "SC_VRS_COMB_MODE_MAX", "value": 3},
{"name": "VRS_COMB_MODE_SATURATE", "value": 4}, {"name": "SC_VRS_COMB_MODE_SATURATE", "value": 4},
] ]
} }

6
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -2240,7 +2240,7 @@ radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer)
/* As the result of min(A, 1x1) or replace(A, 1x1) are always 1x1, set the vertex rate /* As the result of min(A, 1x1) or replace(A, 1x1) are always 1x1, set the vertex rate
* combiner mode as passthrough. * combiner mode as passthrough.
*/ */
pipeline_comb_mode = V_028848_VRS_COMB_MODE_PASSTHRU; pipeline_comb_mode = V_028848_SC_VRS_COMB_MODE_PASSTHRU;
break; break;
case VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX_KHR: case VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX_KHR:
/* The result of max(A, 1x1) is always A. */ /* The result of max(A, 1x1) is always A. */
@@ -2261,11 +2261,11 @@ radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer)
* draw rate and the vertex rate. * draw rate and the vertex rate.
*/ */
if (cmd_buffer->state.mesh_shading) { if (cmd_buffer->state.mesh_shading) {
pa_cl_vrs_cntl |= S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU) | pa_cl_vrs_cntl |= S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_PASSTHRU) |
S_028848_PRIMITIVE_RATE_COMBINER_MODE(pipeline_comb_mode); S_028848_PRIMITIVE_RATE_COMBINER_MODE(pipeline_comb_mode);
} else { } else {
pa_cl_vrs_cntl |= S_028848_VERTEX_RATE_COMBINER_MODE(pipeline_comb_mode) | pa_cl_vrs_cntl |= S_028848_VERTEX_RATE_COMBINER_MODE(pipeline_comb_mode) |
S_028848_PRIMITIVE_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); S_028848_PRIMITIVE_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_PASSTHRU);
} }
/* HTILE_RATE_COMBINER_MODE controls the combiner mode between the primitive rate and the HTILE /* HTILE_RATE_COMBINER_MODE controls the combiner mode between the primitive rate and the HTILE

14
src/amd/vulkan/radv_pipeline.c
View File

@@ -517,7 +517,7 @@ gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
* 16-bit sample coverage mask isn't enough for MSAA8x and * 16-bit sample coverage mask isn't enough for MSAA8x and
* 2x2 coarse shading isn't enough. * 2x2 coarse shading isn't enough.
*/ */
vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE); vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE);
/* Make sure sample shading is enabled even if only MSAA1x is /* Make sure sample shading is enabled even if only MSAA1x is
* used because the SAMPLE_ITER combiner is in passthrough * used because the SAMPLE_ITER combiner is in passthrough
@@ -527,7 +527,7 @@ gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
if (!G_028A4C_PS_ITER_SAMPLE(pipeline->pa_sc_mode_cntl_1)) if (!G_028A4C_PS_ITER_SAMPLE(pipeline->pa_sc_mode_cntl_1))
pipeline->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1); pipeline->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1);
} else { } else {
vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_PASSTHRU);
} }
} }
@@ -4623,7 +4623,7 @@ gfx103_pipeline_emit_vrs_state(struct radeon_cmdbuf *ctx_cs,
const struct vk_graphics_pipeline_state *state) const struct vk_graphics_pipeline_state *state)
{ {
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
uint32_t mode = V_028064_VRS_COMB_MODE_PASSTHRU; uint32_t mode = V_028064_SC_VRS_COMB_MODE_PASSTHRU;
uint8_t rate_x = 0, rate_y = 0; uint8_t rate_x = 0, rate_y = 0;
bool enable_vrs = radv_is_vrs_enabled(pipeline, state); bool enable_vrs = radv_is_vrs_enabled(pipeline, state);
@@ -4631,7 +4631,7 @@ gfx103_pipeline_emit_vrs_state(struct radeon_cmdbuf *ctx_cs,
/* When per-draw VRS is not enabled at all, try enabling VRS coarse shading 2x2 if the driver /* When per-draw VRS is not enabled at all, try enabling VRS coarse shading 2x2 if the driver
* determined that it's safe to enable. * determined that it's safe to enable.
*/ */
mode = V_028064_VRS_COMB_MODE_OVERRIDE; mode = V_028064_SC_VRS_COMB_MODE_OVERRIDE;
rate_x = rate_y = 1; rate_x = rate_y = 1;
} else if (!radv_is_static_vrs_enabled(pipeline, state) && pipeline->force_vrs_per_vertex && } else if (!radv_is_static_vrs_enabled(pipeline, state) && pipeline->force_vrs_per_vertex &&
get_vs_output_info(pipeline)->writes_primitive_shading_rate) { get_vs_output_info(pipeline)->writes_primitive_shading_rate) {
@@ -4640,15 +4640,15 @@ gfx103_pipeline_emit_vrs_state(struct radeon_cmdbuf *ctx_cs,
* in DX12 it's fully dynamic. * in DX12 it's fully dynamic.
*/ */
radeon_set_context_reg(ctx_cs, R_028848_PA_CL_VRS_CNTL, radeon_set_context_reg(ctx_cs, R_028848_PA_CL_VRS_CNTL,
S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE) | S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) |
S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE)); S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
/* If the shader is using discard, turn off coarse shading because discard at 2x2 pixel /* If the shader is using discard, turn off coarse shading because discard at 2x2 pixel
* granularity degrades quality too much. MIN allows sample shading but not coarse shading. * granularity degrades quality too much. MIN allows sample shading but not coarse shading.
*/ */
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
mode = ps->info.ps.can_discard ? V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU; mode = ps->info.ps.can_discard ? V_028064_SC_VRS_COMB_MODE_MIN : V_028064_SC_VRS_COMB_MODE_PASSTHRU;
} }
if (pdevice->rad_info.gfx_level >= GFX11) { if (pdevice->rad_info.gfx_level >= GFX11) {

2
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -504,7 +504,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
/* This allows sample shading. */ /* This allows sample shading. */
radeon_set_context_reg( radeon_set_context_reg(
cs, R_028848_PA_CL_VRS_CNTL, cs, R_028848_PA_CL_VRS_CNTL,
S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE)); S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
} }
} }

8
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -1621,7 +1621,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL, radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE( S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(
V_028064_VRS_COMB_MODE_OVERRIDE) | V_028064_SC_VRS_COMB_MODE_OVERRIDE) |
S_028064_VRS_OVERRIDE_RATE_X(1) | S_028064_VRS_OVERRIDE_RATE_X(1) |
S_028064_VRS_OVERRIDE_RATE_Y(1)); S_028064_VRS_OVERRIDE_RATE_Y(1));
} }
@@ -1641,7 +1641,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
S_0283D0_VRS_RATE(V_0283D0_VRS_SHADING_RATE_1X1)); S_0283D0_VRS_RATE(V_0283D0_VRS_SHADING_RATE_1X1));
} else { } else {
unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ? unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU; V_028064_SC_VRS_COMB_MODE_MIN : V_028064_SC_VRS_COMB_MODE_PASSTHRU;
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL, radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
@@ -5923,8 +5923,8 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
* (e.g. enabled sample shading overrides the vertex rate) * (e.g. enabled sample shading overrides the vertex rate)
*/ */
si_pm4_set_reg(pm4, R_028848_PA_CL_VRS_CNTL, si_pm4_set_reg(pm4, R_028848_PA_CL_VRS_CNTL,
S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE) | S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) |
S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE)); S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
} }
if (sctx->gfx_level >= GFX11) { if (sctx->gfx_level >= GFX11) {