i965: Hide the register type hardware encodings
So we stop mixing them with the logical enum. Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
This commit is contained in:
@@ -819,37 +819,6 @@ enum PACKED brw_reg_file {
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BAD_FILE,
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};
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enum hw_reg_type {
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BRW_HW_REG_TYPE_UD = 0,
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BRW_HW_REG_TYPE_D = 1,
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BRW_HW_REG_TYPE_UW = 2,
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BRW_HW_REG_TYPE_W = 3,
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BRW_HW_REG_TYPE_F = 7,
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GEN8_HW_REG_TYPE_UQ = 8,
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GEN8_HW_REG_TYPE_Q = 9,
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BRW_HW_REG_TYPE_UB = 4,
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BRW_HW_REG_TYPE_B = 5,
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GEN7_HW_REG_TYPE_DF = 6,
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GEN8_HW_REG_TYPE_HF = 10,
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};
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enum hw_imm_type {
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BRW_HW_IMM_TYPE_UD = 0,
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BRW_HW_IMM_TYPE_D = 1,
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BRW_HW_IMM_TYPE_UW = 2,
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BRW_HW_IMM_TYPE_W = 3,
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BRW_HW_IMM_TYPE_F = 7,
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GEN8_HW_IMM_TYPE_UQ = 8,
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GEN8_HW_IMM_TYPE_Q = 9,
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BRW_HW_IMM_TYPE_UV = 4, /* Gen6+ packed unsigned immediate vector */
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BRW_HW_IMM_TYPE_VF = 5, /* packed float immediate vector */
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BRW_HW_IMM_TYPE_V = 6, /* packed int imm. vector; uword dest only */
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GEN8_HW_IMM_TYPE_DF = 10,
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GEN8_HW_IMM_TYPE_HF = 11,
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};
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/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
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* the types were implied. IVB adds BFE and BFI2 that operate on doublewords
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* and unsigned doublewords, so a new field is also available in the da3src
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@@ -27,6 +27,37 @@
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#define INVALID (-1)
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enum hw_reg_type {
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BRW_HW_REG_TYPE_UD = 0,
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BRW_HW_REG_TYPE_D = 1,
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BRW_HW_REG_TYPE_UW = 2,
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BRW_HW_REG_TYPE_W = 3,
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BRW_HW_REG_TYPE_F = 7,
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GEN8_HW_REG_TYPE_UQ = 8,
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GEN8_HW_REG_TYPE_Q = 9,
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BRW_HW_REG_TYPE_UB = 4,
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BRW_HW_REG_TYPE_B = 5,
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GEN7_HW_REG_TYPE_DF = 6,
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GEN8_HW_REG_TYPE_HF = 10,
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};
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enum hw_imm_type {
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BRW_HW_IMM_TYPE_UD = 0,
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BRW_HW_IMM_TYPE_D = 1,
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BRW_HW_IMM_TYPE_UW = 2,
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BRW_HW_IMM_TYPE_W = 3,
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BRW_HW_IMM_TYPE_F = 7,
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GEN8_HW_IMM_TYPE_UQ = 8,
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GEN8_HW_IMM_TYPE_Q = 9,
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BRW_HW_IMM_TYPE_UV = 4,
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BRW_HW_IMM_TYPE_VF = 5,
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BRW_HW_IMM_TYPE_V = 6,
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GEN8_HW_IMM_TYPE_DF = 10,
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GEN8_HW_IMM_TYPE_HF = 11,
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};
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static const struct {
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enum hw_reg_type reg_type;
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enum hw_imm_type imm_type;
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