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radv: only emit PGM_LO for the vertex prolog

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Shaders are allocated in the 32-bit address space.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13551>
This commit is contained in:
Samuel Pitoiset
2021-10-15 12:18:43 +02:00
committed by Marge Bot
parent 824ce4ef40
commit e04101c34e
2 changed files with 4 additions and 3 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
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@@ -2894,9 +2894,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shad
rsrc1_reg = R_00B328_SPI_SHADER_PGM_RSRC1_ES;
}
radeon_set_sh_reg_seq(cmd_buffer->cs, pgm_lo_reg, 2);
radeon_emit(cmd_buffer->cs, prolog_va >> 8);
radeon_emit(cmd_buffer->cs, S_00B124_MEM_BASE(prolog_va >> 40));
radeon_set_sh_reg(cmd_buffer->cs, pgm_lo_reg, prolog_va >> 8);
if (chip < GFX10)
radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1);

3
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -310,6 +310,9 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
}
radeon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS,
S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
unsigned cu_mask_ps = 0xffffffff;
/* It's wasteful to enable all CUs for PS if shader arrays have a