freedreno: Generate headers from xml files
Reviewed-by: Eric Engestrom <eric@engestrom.ch> Acked-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Kristian H. Kristensen
committed by
Kristian H. Kristensen
Kristian H. Kristensen
parent
51e2124a4b
commit
e03259974e
@@ -28,3 +28,4 @@ include $(LOCAL_PATH)/Makefile.sources
|
||||
include $(MESA_TOP)/src/gallium/drivers/freedreno/Android.gen.mk
|
||||
include $(LOCAL_PATH)/Android.drm.mk
|
||||
include $(LOCAL_PATH)/Android.ir3.mk
|
||||
include $(LOCAL_PATH)/Android.registers.mk
|
||||
|
||||
58
src/freedreno/Android.registers.mk
Normal file
58
src/freedreno/Android.registers.mk
Normal file
@@ -0,0 +1,58 @@
|
||||
# Mesa 3-D graphics library
|
||||
#
|
||||
# Copyright (C)
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
# and/or sell copies of the Software, and to permit persons to whom the
|
||||
# Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included
|
||||
# in all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
# DEALINGS IN THE SOFTWARE.
|
||||
|
||||
# Android.mk for libfreedreno_registers.a
|
||||
|
||||
# ---------------------------------------
|
||||
# Build libfreedreno_registers
|
||||
# ---------------------------------------
|
||||
|
||||
include $(CLEAR_VARS)
|
||||
|
||||
LOCAL_MODULE := libfreedreno_registers
|
||||
|
||||
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
|
||||
|
||||
intermediates := $(call local-generated-sources-dir)
|
||||
|
||||
# dummy.c source file is generated to meet the build system's rules.
|
||||
LOCAL_GENERATED_SOURCES += $(intermediates)/dummy.c
|
||||
|
||||
$(intermediates)/dummy.c:
|
||||
@mkdir -p $(dir $@)
|
||||
@echo "Gen Dummy: $(PRIVATE_MODULE) <= $(notdir $(@))"
|
||||
$(hide) touch $@
|
||||
|
||||
# This is the list of auto-generated files headers
|
||||
LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/registers/, \
|
||||
a2xx.xml.h a3xx.xml.h a4xx.xml.h a5xx.xml.h a6xx.xml.h adreno_common.xml.h adreno_pm4.xml.h)
|
||||
|
||||
$(intermediates)/registers/%.xml.h: $(LOCAL_PATH)/registers/%.xml $(LOCAL_PATH)/registers/gen_header.py
|
||||
@mkdir -p $(dir $@)
|
||||
@echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
|
||||
$(hide) $(MESA_PYTHON2) $(LOCAL_PATH)/registers/gen_header.py $< > $@
|
||||
|
||||
LOCAL_EXPORT_C_INCLUDE_DIRS := \
|
||||
$(intermediates)
|
||||
|
||||
include $(MESA_COMMON_MK)
|
||||
include $(BUILD_STATIC_LIBRARY)
|
||||
@@ -49,12 +49,3 @@ ir3_SOURCES := \
|
||||
|
||||
ir3_GENERATED_FILES := \
|
||||
ir3/ir3_nir_trig.c
|
||||
|
||||
registers_FILES := \
|
||||
registers/a2xx.xml.h \
|
||||
registers/a3xx.xml.h \
|
||||
registers/a4xx.xml.h \
|
||||
registers/a5xx.xml.h \
|
||||
registers/a6xx.xml.h \
|
||||
registers/adreno_common.xml.h \
|
||||
registers/adreno_pm4.xml.h
|
||||
|
||||
@@ -22,6 +22,7 @@ inc_freedreno = include_directories(['.', './registers'])
|
||||
|
||||
subdir('drm')
|
||||
subdir('ir3')
|
||||
subdir('registers')
|
||||
|
||||
if with_freedreno_vk
|
||||
subdir('vulkan')
|
||||
|
||||
1650
src/freedreno/registers/a2xx.xml
Normal file
1650
src/freedreno/registers/a2xx.xml
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
1754
src/freedreno/registers/a3xx.xml
Normal file
1754
src/freedreno/registers/a3xx.xml
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2391
src/freedreno/registers/a4xx.xml
Normal file
2391
src/freedreno/registers/a4xx.xml
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2987
src/freedreno/registers/a5xx.xml
Normal file
2987
src/freedreno/registers/a5xx.xml
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
3311
src/freedreno/registers/a6xx.xml
Normal file
3311
src/freedreno/registers/a6xx.xml
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
368
src/freedreno/registers/adreno_common.xml
Normal file
368
src/freedreno/registers/adreno_common.xml
Normal file
@@ -0,0 +1,368 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<database xmlns="http://nouveau.freedesktop.org/"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||
|
||||
<enum name="chip" bare="yes">
|
||||
<value name="A2XX"/>
|
||||
<value name="A3XX"/>
|
||||
<value name="A4XX"/>
|
||||
<value name="A5XX"/>
|
||||
<value name="A6XX"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_pa_su_sc_draw">
|
||||
<value name="PC_DRAW_POINTS" value="0"/>
|
||||
<value name="PC_DRAW_LINES" value="1"/>
|
||||
<value name="PC_DRAW_TRIANGLES" value="2"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_compare_func">
|
||||
<value name="FUNC_NEVER" value="0"/>
|
||||
<value name="FUNC_LESS" value="1"/>
|
||||
<value name="FUNC_EQUAL" value="2"/>
|
||||
<value name="FUNC_LEQUAL" value="3"/>
|
||||
<value name="FUNC_GREATER" value="4"/>
|
||||
<value name="FUNC_NOTEQUAL" value="5"/>
|
||||
<value name="FUNC_GEQUAL" value="6"/>
|
||||
<value name="FUNC_ALWAYS" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_stencil_op">
|
||||
<value name="STENCIL_KEEP" value="0"/>
|
||||
<value name="STENCIL_ZERO" value="1"/>
|
||||
<value name="STENCIL_REPLACE" value="2"/>
|
||||
<value name="STENCIL_INCR_CLAMP" value="3"/>
|
||||
<value name="STENCIL_DECR_CLAMP" value="4"/>
|
||||
<value name="STENCIL_INVERT" value="5"/>
|
||||
<value name="STENCIL_INCR_WRAP" value="6"/>
|
||||
<value name="STENCIL_DECR_WRAP" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_rb_blend_factor">
|
||||
<value name="FACTOR_ZERO" value="0"/>
|
||||
<value name="FACTOR_ONE" value="1"/>
|
||||
<value name="FACTOR_SRC_COLOR" value="4"/>
|
||||
<value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/>
|
||||
<value name="FACTOR_SRC_ALPHA" value="6"/>
|
||||
<value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/>
|
||||
<value name="FACTOR_DST_COLOR" value="8"/>
|
||||
<value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/>
|
||||
<value name="FACTOR_DST_ALPHA" value="10"/>
|
||||
<value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/>
|
||||
<value name="FACTOR_CONSTANT_COLOR" value="12"/>
|
||||
<value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/>
|
||||
<value name="FACTOR_CONSTANT_ALPHA" value="14"/>
|
||||
<value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/>
|
||||
<value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/>
|
||||
<value name="FACTOR_SRC1_COLOR" value="20"/>
|
||||
<value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/>
|
||||
<value name="FACTOR_SRC1_ALPHA" value="22"/>
|
||||
<value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/>
|
||||
</enum>
|
||||
|
||||
<bitset name="adreno_rb_stencilrefmask" inline="yes">
|
||||
<bitfield name="STENCILREF" low="0" high="7" type="hex"/>
|
||||
<bitfield name="STENCILMASK" low="8" high="15" type="hex"/>
|
||||
<bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/>
|
||||
</bitset>
|
||||
|
||||
<enum name="adreno_rb_surface_endian">
|
||||
<value name="ENDIAN_NONE" value="0"/>
|
||||
<value name="ENDIAN_8IN16" value="1"/>
|
||||
<value name="ENDIAN_8IN32" value="2"/>
|
||||
<value name="ENDIAN_16IN32" value="3"/>
|
||||
<value name="ENDIAN_8IN64" value="4"/>
|
||||
<value name="ENDIAN_8IN128" value="5"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_rb_dither_mode">
|
||||
<value name="DITHER_DISABLE" value="0"/>
|
||||
<value name="DITHER_ALWAYS" value="1"/>
|
||||
<value name="DITHER_IF_ALPHA_OFF" value="2"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_rb_depth_format">
|
||||
<value name="DEPTHX_16" value="0"/>
|
||||
<value name="DEPTHX_24_8" value="1"/>
|
||||
<value name="DEPTHX_32" value="2"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_rb_copy_control_mode">
|
||||
<value name="RB_COPY_RESOLVE" value="1"/>
|
||||
<value name="RB_COPY_CLEAR" value="2"/>
|
||||
<value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? -->
|
||||
</enum>
|
||||
|
||||
<bitset name="adreno_reg_xy" inline="yes">
|
||||
<bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/>
|
||||
<bitfield name="X" low="0" high="14" type="uint"/>
|
||||
<bitfield name="Y" low="16" high="30" type="uint"/>
|
||||
</bitset>
|
||||
|
||||
<bitset name="adreno_cp_protect" inline="yes">
|
||||
<bitfield name="BASE_ADDR" low="0" high="16"/>
|
||||
<bitfield name="MASK_LEN" low="24" high="28"/>
|
||||
<bitfield name="TRAP_WRITE" pos="29"/>
|
||||
<bitfield name="TRAP_READ" pos="30"/>
|
||||
</bitset>
|
||||
|
||||
<domain name="AXXX" width="32">
|
||||
<brief>Registers in common between a2xx and a3xx</brief>
|
||||
|
||||
<reg32 offset="0x01c0" name="CP_RB_BASE"/>
|
||||
<reg32 offset="0x01c1" name="CP_RB_CNTL">
|
||||
<bitfield name="BUFSZ" low="0" high="5"/>
|
||||
<bitfield name="BLKSZ" low="8" high="13"/>
|
||||
<bitfield name="BUF_SWAP" low="16" high="17"/>
|
||||
<bitfield name="POLL_EN" pos="20" type="boolean"/>
|
||||
<bitfield name="NO_UPDATE" pos="27" type="boolean"/>
|
||||
<bitfield name="RPTR_WR_EN" pos="31" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR">
|
||||
<bitfield name="SWAP" low="0" high="1" type="uint"/>
|
||||
<bitfield name="ADDR" low="2" high="31" shr="2"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/>
|
||||
<reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/>
|
||||
<reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/>
|
||||
<reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/>
|
||||
<reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/>
|
||||
<reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS">
|
||||
<bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/>
|
||||
<bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/>
|
||||
<bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS">
|
||||
<bitfield name="MEQ_END" low="16" high="20" type="uint"/>
|
||||
<bitfield name="ROQ_END" low="24" high="28" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01d7" name="CP_CSQ_AVAIL">
|
||||
<bitfield name="RING" low="0" high="6" type="uint"/>
|
||||
<bitfield name="IB1" low="8" high="14" type="uint"/>
|
||||
<bitfield name="IB2" low="16" high="22" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01d8" name="CP_STQ_AVAIL">
|
||||
<bitfield name="ST" low="0" high="6" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01d9" name="CP_MEQ_AVAIL">
|
||||
<bitfield name="MEQ" low="0" high="4" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01dc" name="SCRATCH_UMSK">
|
||||
<bitfield name="UMSK" low="0" high="7" type="uint"/>
|
||||
<bitfield name="SWAP" low="16" high="17" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01dd" name="SCRATCH_ADDR"/>
|
||||
<reg32 offset="0x01ea" name="CP_ME_RDADDR"/>
|
||||
|
||||
<reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/>
|
||||
<reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/>
|
||||
<reg32 offset="0x01f2" name="CP_INT_CNTL">
|
||||
<bitfield name="SW_INT_MASK" pos="19" type="boolean"/>
|
||||
<bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/>
|
||||
<bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/>
|
||||
<bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/>
|
||||
<bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/>
|
||||
<bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/>
|
||||
<bitfield name="IB2_INT_MASK" pos="29" type="boolean"/>
|
||||
<bitfield name="IB1_INT_MASK" pos="30" type="boolean"/>
|
||||
<bitfield name="RB_INT_MASK" pos="31" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01f3" name="CP_INT_STATUS"/>
|
||||
<reg32 offset="0x01f4" name="CP_INT_ACK"/>
|
||||
<reg32 offset="0x01f6" name="CP_ME_CNTL">
|
||||
<bitfield name="BUSY" pos="29" type="boolean"/>
|
||||
<bitfield name="HALT" pos="28" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01f7" name="CP_ME_STATUS"/>
|
||||
<reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/>
|
||||
<reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/>
|
||||
<reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/>
|
||||
<reg32 offset="0x01fc" name="CP_DEBUG">
|
||||
<bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/>
|
||||
<bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/>
|
||||
<bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/>
|
||||
<bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/>
|
||||
<bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/>
|
||||
<bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/>
|
||||
<bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/>
|
||||
<bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01fd" name="CP_CSQ_RB_STAT">
|
||||
<bitfield name="RPTR" low="0" high="6" type="uint"/>
|
||||
<bitfield name="WPTR" low="16" high="22" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT">
|
||||
<bitfield name="RPTR" low="0" high="6" type="uint"/>
|
||||
<bitfield name="WPTR" low="16" high="22" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT">
|
||||
<bitfield name="RPTR" low="0" high="6" type="uint"/>
|
||||
<bitfield name="WPTR" low="16" high="22" type="uint"/>
|
||||
</reg32>
|
||||
|
||||
<reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/>
|
||||
<reg32 offset="0x0443" name="CP_STQ_ST_STAT"/>
|
||||
<reg32 offset="0x044d" name="CP_ST_BASE"/>
|
||||
<reg32 offset="0x044e" name="CP_ST_BUFSZ"/>
|
||||
<reg32 offset="0x044f" name="CP_MEQ_STAT"/>
|
||||
<reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/>
|
||||
<reg32 offset="0x0454" name="CP_BIN_MASK_LO"/>
|
||||
<reg32 offset="0x0455" name="CP_BIN_MASK_HI"/>
|
||||
<reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/>
|
||||
<reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/>
|
||||
<reg32 offset="0x0458" name="CP_IB1_BASE"/>
|
||||
<reg32 offset="0x0459" name="CP_IB1_BUFSZ"/>
|
||||
<reg32 offset="0x045a" name="CP_IB2_BASE"/>
|
||||
<reg32 offset="0x045b" name="CP_IB2_BUFSZ"/>
|
||||
<reg32 offset="0x047f" name="CP_STAT">
|
||||
<bitfield pos="31" name="CP_BUSY"/>
|
||||
<bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/>
|
||||
<bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/>
|
||||
<bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/>
|
||||
<bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/>
|
||||
<bitfield pos="26" name="ME_BUSY"/>
|
||||
<bitfield pos="25" name="MIU_WR_C_BUSY"/>
|
||||
<bitfield pos="23" name="CP_3D_BUSY"/>
|
||||
<bitfield pos="22" name="CP_NRT_BUSY"/>
|
||||
<bitfield pos="21" name="RBIU_SCRATCH_BUSY"/>
|
||||
<bitfield pos="20" name="RCIU_ME_BUSY"/>
|
||||
<bitfield pos="19" name="RCIU_PFP_BUSY"/>
|
||||
<bitfield pos="18" name="MEQ_RING_BUSY"/>
|
||||
<bitfield pos="17" name="PFP_BUSY"/>
|
||||
<bitfield pos="16" name="ST_QUEUE_BUSY"/>
|
||||
<bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/>
|
||||
<bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/>
|
||||
<bitfield pos="11" name="RING_QUEUE_BUSY"/>
|
||||
<bitfield pos="10" name="CSF_BUSY"/>
|
||||
<bitfield pos="9" name="CSF_ST_BUSY"/>
|
||||
<bitfield pos="8" name="EVENT_BUSY"/>
|
||||
<bitfield pos="7" name="CSF_INDIRECT2_BUSY"/>
|
||||
<bitfield pos="6" name="CSF_INDIRECTS_BUSY"/>
|
||||
<bitfield pos="5" name="CSF_RING_BUSY"/>
|
||||
<bitfield pos="4" name="RCIU_BUSY"/>
|
||||
<bitfield pos="3" name="RBIU_BUSY"/>
|
||||
<bitfield pos="2" name="MIU_RD_RETURN_BUSY"/>
|
||||
<bitfield pos="1" name="MIU_RD_REQ_BUSY"/>
|
||||
<bitfield pos="0" name="MIU_WR_BUSY"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/>
|
||||
<reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/>
|
||||
<reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/>
|
||||
<reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/>
|
||||
<reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/>
|
||||
<reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/>
|
||||
<reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/>
|
||||
<reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/>
|
||||
|
||||
<reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/>
|
||||
<reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/>
|
||||
<reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/>
|
||||
<reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/>
|
||||
<reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/>
|
||||
<reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/>
|
||||
<reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/>
|
||||
<reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/>
|
||||
<reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/>
|
||||
<reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/>
|
||||
<reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/>
|
||||
<reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/>
|
||||
<reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/>
|
||||
<reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/>
|
||||
<reg32 offset="0x060e" name="CP_ME_NRT_DATA"/>
|
||||
<reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/>
|
||||
<reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/>
|
||||
<reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/>
|
||||
|
||||
</domain>
|
||||
|
||||
<!--
|
||||
Common between A3xx and A4xx:
|
||||
-->
|
||||
|
||||
<enum name="a3xx_regid">
|
||||
<value name="REGID_UNUSED" value="0xfc"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_rop_code">
|
||||
<value name="ROP_CLEAR" value="0"/>
|
||||
<value name="ROP_NOR" value="1"/>
|
||||
<value name="ROP_AND_INVERTED" value="2"/>
|
||||
<value name="ROP_COPY_INVERTED" value="3"/>
|
||||
<value name="ROP_AND_REVERSE" value="4"/>
|
||||
<value name="ROP_INVERT" value="5"/>
|
||||
<value name="ROP_XOR" value="6"/>
|
||||
<value name="ROP_NAND" value="7"/>
|
||||
<value name="ROP_AND" value="8"/>
|
||||
<value name="ROP_EQUIV" value="9"/>
|
||||
<value name="ROP_NOOP" value="10"/>
|
||||
<value name="ROP_OR_INVERTED" value="11"/>
|
||||
<value name="ROP_COPY" value="12"/>
|
||||
<value name="ROP_OR_REVERSE" value="13"/>
|
||||
<value name="ROP_OR" value="14"/>
|
||||
<value name="ROP_SET" value="15"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_render_mode">
|
||||
<value name="RB_RENDERING_PASS" value="0"/>
|
||||
<value name="RB_TILING_PASS" value="1"/>
|
||||
<value name="RB_RESOLVE_PASS" value="2"/>
|
||||
<value name="RB_COMPUTE_PASS" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_msaa_samples">
|
||||
<value name="MSAA_ONE" value="0"/>
|
||||
<value name="MSAA_TWO" value="1"/>
|
||||
<value name="MSAA_FOUR" value="2"/>
|
||||
<value name="MSAA_EIGHT" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_threadmode">
|
||||
<value value="0" name="MULTI"/>
|
||||
<value value="1" name="SINGLE"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_instrbuffermode">
|
||||
<!--
|
||||
When shader size goes above ~128 or so, blob switches to '0'
|
||||
and doesn't emit shader in cmdstream. When either is '0' it
|
||||
doesn't get emitted via CP_LOAD_STATE. When only one is
|
||||
'0' the other gets size 256-others_size. So I think that:
|
||||
BUFFER => execute out of state memory
|
||||
CACHE => use available state memory as local cache
|
||||
NOTE that when CACHE mode, also set CACHEINVALID flag!
|
||||
|
||||
TODO check if that 256 size is same for all a3xx
|
||||
-->
|
||||
<value value="0" name="CACHE"/>
|
||||
<value value="1" name="BUFFER"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_threadsize">
|
||||
<value value="0" name="TWO_QUADS"/>
|
||||
<value value="1" name="FOUR_QUADS"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_color_swap">
|
||||
<value name="WZYX" value="0"/>
|
||||
<value name="WXYZ" value="1"/>
|
||||
<value name="ZYXW" value="2"/>
|
||||
<value name="XYZW" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a3xx_rb_blend_opcode">
|
||||
<value name="BLEND_DST_PLUS_SRC" value="0"/>
|
||||
<value name="BLEND_SRC_MINUS_DST" value="1"/>
|
||||
<value name="BLEND_DST_MINUS_SRC" value="2"/>
|
||||
<value name="BLEND_MIN_DST_SRC" value="3"/>
|
||||
<value name="BLEND_MAX_DST_SRC" value="4"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a4xx_tess_spacing">
|
||||
<value name="EQUAL_SPACING" value="0"/>
|
||||
<value name="ODD_SPACING" value="2"/>
|
||||
<value name="EVEN_SPACING" value="3"/>
|
||||
</enum>
|
||||
|
||||
</database>
|
||||
|
||||
@@ -1,536 +0,0 @@
|
||||
#ifndef ADRENO_COMMON_XML
|
||||
#define ADRENO_COMMON_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
enum chip {
|
||||
A2XX = 0,
|
||||
A3XX = 0,
|
||||
A4XX = 0,
|
||||
A5XX = 0,
|
||||
A6XX = 0,
|
||||
};
|
||||
|
||||
enum adreno_pa_su_sc_draw {
|
||||
PC_DRAW_POINTS = 0,
|
||||
PC_DRAW_LINES = 1,
|
||||
PC_DRAW_TRIANGLES = 2,
|
||||
};
|
||||
|
||||
enum adreno_compare_func {
|
||||
FUNC_NEVER = 0,
|
||||
FUNC_LESS = 1,
|
||||
FUNC_EQUAL = 2,
|
||||
FUNC_LEQUAL = 3,
|
||||
FUNC_GREATER = 4,
|
||||
FUNC_NOTEQUAL = 5,
|
||||
FUNC_GEQUAL = 6,
|
||||
FUNC_ALWAYS = 7,
|
||||
};
|
||||
|
||||
enum adreno_stencil_op {
|
||||
STENCIL_KEEP = 0,
|
||||
STENCIL_ZERO = 1,
|
||||
STENCIL_REPLACE = 2,
|
||||
STENCIL_INCR_CLAMP = 3,
|
||||
STENCIL_DECR_CLAMP = 4,
|
||||
STENCIL_INVERT = 5,
|
||||
STENCIL_INCR_WRAP = 6,
|
||||
STENCIL_DECR_WRAP = 7,
|
||||
};
|
||||
|
||||
enum adreno_rb_blend_factor {
|
||||
FACTOR_ZERO = 0,
|
||||
FACTOR_ONE = 1,
|
||||
FACTOR_SRC_COLOR = 4,
|
||||
FACTOR_ONE_MINUS_SRC_COLOR = 5,
|
||||
FACTOR_SRC_ALPHA = 6,
|
||||
FACTOR_ONE_MINUS_SRC_ALPHA = 7,
|
||||
FACTOR_DST_COLOR = 8,
|
||||
FACTOR_ONE_MINUS_DST_COLOR = 9,
|
||||
FACTOR_DST_ALPHA = 10,
|
||||
FACTOR_ONE_MINUS_DST_ALPHA = 11,
|
||||
FACTOR_CONSTANT_COLOR = 12,
|
||||
FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
|
||||
FACTOR_CONSTANT_ALPHA = 14,
|
||||
FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
|
||||
FACTOR_SRC_ALPHA_SATURATE = 16,
|
||||
FACTOR_SRC1_COLOR = 20,
|
||||
FACTOR_ONE_MINUS_SRC1_COLOR = 21,
|
||||
FACTOR_SRC1_ALPHA = 22,
|
||||
FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
|
||||
};
|
||||
|
||||
enum adreno_rb_surface_endian {
|
||||
ENDIAN_NONE = 0,
|
||||
ENDIAN_8IN16 = 1,
|
||||
ENDIAN_8IN32 = 2,
|
||||
ENDIAN_16IN32 = 3,
|
||||
ENDIAN_8IN64 = 4,
|
||||
ENDIAN_8IN128 = 5,
|
||||
};
|
||||
|
||||
enum adreno_rb_dither_mode {
|
||||
DITHER_DISABLE = 0,
|
||||
DITHER_ALWAYS = 1,
|
||||
DITHER_IF_ALPHA_OFF = 2,
|
||||
};
|
||||
|
||||
enum adreno_rb_depth_format {
|
||||
DEPTHX_16 = 0,
|
||||
DEPTHX_24_8 = 1,
|
||||
DEPTHX_32 = 2,
|
||||
};
|
||||
|
||||
enum adreno_rb_copy_control_mode {
|
||||
RB_COPY_RESOLVE = 1,
|
||||
RB_COPY_CLEAR = 2,
|
||||
RB_COPY_DEPTH_STENCIL = 5,
|
||||
};
|
||||
|
||||
enum a3xx_rop_code {
|
||||
ROP_CLEAR = 0,
|
||||
ROP_NOR = 1,
|
||||
ROP_AND_INVERTED = 2,
|
||||
ROP_COPY_INVERTED = 3,
|
||||
ROP_AND_REVERSE = 4,
|
||||
ROP_INVERT = 5,
|
||||
ROP_XOR = 6,
|
||||
ROP_NAND = 7,
|
||||
ROP_AND = 8,
|
||||
ROP_EQUIV = 9,
|
||||
ROP_NOOP = 10,
|
||||
ROP_OR_INVERTED = 11,
|
||||
ROP_COPY = 12,
|
||||
ROP_OR_REVERSE = 13,
|
||||
ROP_OR = 14,
|
||||
ROP_SET = 15,
|
||||
};
|
||||
|
||||
enum a3xx_render_mode {
|
||||
RB_RENDERING_PASS = 0,
|
||||
RB_TILING_PASS = 1,
|
||||
RB_RESOLVE_PASS = 2,
|
||||
RB_COMPUTE_PASS = 3,
|
||||
};
|
||||
|
||||
enum a3xx_msaa_samples {
|
||||
MSAA_ONE = 0,
|
||||
MSAA_TWO = 1,
|
||||
MSAA_FOUR = 2,
|
||||
MSAA_EIGHT = 3,
|
||||
};
|
||||
|
||||
enum a3xx_threadmode {
|
||||
MULTI = 0,
|
||||
SINGLE = 1,
|
||||
};
|
||||
|
||||
enum a3xx_instrbuffermode {
|
||||
CACHE = 0,
|
||||
BUFFER = 1,
|
||||
};
|
||||
|
||||
enum a3xx_threadsize {
|
||||
TWO_QUADS = 0,
|
||||
FOUR_QUADS = 1,
|
||||
};
|
||||
|
||||
enum a3xx_color_swap {
|
||||
WZYX = 0,
|
||||
WXYZ = 1,
|
||||
ZYXW = 2,
|
||||
XYZW = 3,
|
||||
};
|
||||
|
||||
enum a3xx_rb_blend_opcode {
|
||||
BLEND_DST_PLUS_SRC = 0,
|
||||
BLEND_SRC_MINUS_DST = 1,
|
||||
BLEND_DST_MINUS_SRC = 2,
|
||||
BLEND_MIN_DST_SRC = 3,
|
||||
BLEND_MAX_DST_SRC = 4,
|
||||
};
|
||||
|
||||
enum a4xx_tess_spacing {
|
||||
EQUAL_SPACING = 0,
|
||||
ODD_SPACING = 2,
|
||||
EVEN_SPACING = 3,
|
||||
};
|
||||
|
||||
#define REG_AXXX_CP_RB_BASE 0x000001c0
|
||||
|
||||
#define REG_AXXX_CP_RB_CNTL 0x000001c1
|
||||
#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
|
||||
#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
|
||||
#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
|
||||
static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
|
||||
#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
|
||||
#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
|
||||
#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
|
||||
|
||||
#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
|
||||
#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
|
||||
#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
|
||||
#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
|
||||
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
|
||||
{
|
||||
assert(!(val & 0x3));
|
||||
return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_RB_RPTR 0x000001c4
|
||||
|
||||
#define REG_AXXX_CP_RB_WPTR 0x000001c5
|
||||
|
||||
#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
|
||||
|
||||
#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
|
||||
|
||||
#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
|
||||
|
||||
#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
|
||||
}
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
|
||||
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
|
||||
}
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
|
||||
}
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
|
||||
static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
|
||||
#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
|
||||
#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
|
||||
static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_STQ_AVAIL 0x000001d8
|
||||
#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
|
||||
#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
|
||||
#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
|
||||
#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_SCRATCH_UMSK 0x000001dc
|
||||
#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
|
||||
#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
|
||||
static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
|
||||
}
|
||||
#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
|
||||
#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
|
||||
static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_SCRATCH_ADDR 0x000001dd
|
||||
|
||||
#define REG_AXXX_CP_ME_RDADDR 0x000001ea
|
||||
|
||||
#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
|
||||
|
||||
#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
|
||||
|
||||
#define REG_AXXX_CP_INT_CNTL 0x000001f2
|
||||
#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000
|
||||
#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000
|
||||
#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000
|
||||
#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000
|
||||
#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000
|
||||
#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000
|
||||
#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000
|
||||
#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000
|
||||
#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000
|
||||
|
||||
#define REG_AXXX_CP_INT_STATUS 0x000001f3
|
||||
|
||||
#define REG_AXXX_CP_INT_ACK 0x000001f4
|
||||
|
||||
#define REG_AXXX_CP_ME_CNTL 0x000001f6
|
||||
#define AXXX_CP_ME_CNTL_BUSY 0x20000000
|
||||
#define AXXX_CP_ME_CNTL_HALT 0x10000000
|
||||
|
||||
#define REG_AXXX_CP_ME_STATUS 0x000001f7
|
||||
|
||||
#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
|
||||
|
||||
#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
|
||||
|
||||
#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
|
||||
|
||||
#define REG_AXXX_CP_DEBUG 0x000001fc
|
||||
#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
|
||||
#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
|
||||
#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
|
||||
#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
|
||||
#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
|
||||
#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
|
||||
#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
|
||||
#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
|
||||
|
||||
#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
|
||||
#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
|
||||
#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
|
||||
#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
|
||||
|
||||
#define REG_AXXX_CP_STQ_ST_STAT 0x00000443
|
||||
|
||||
#define REG_AXXX_CP_ST_BASE 0x0000044d
|
||||
|
||||
#define REG_AXXX_CP_ST_BUFSZ 0x0000044e
|
||||
|
||||
#define REG_AXXX_CP_MEQ_STAT 0x0000044f
|
||||
|
||||
#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
|
||||
|
||||
#define REG_AXXX_CP_BIN_MASK_LO 0x00000454
|
||||
|
||||
#define REG_AXXX_CP_BIN_MASK_HI 0x00000455
|
||||
|
||||
#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
|
||||
|
||||
#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
|
||||
|
||||
#define REG_AXXX_CP_IB1_BASE 0x00000458
|
||||
|
||||
#define REG_AXXX_CP_IB1_BUFSZ 0x00000459
|
||||
|
||||
#define REG_AXXX_CP_IB2_BASE 0x0000045a
|
||||
|
||||
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
|
||||
|
||||
#define REG_AXXX_CP_STAT 0x0000047f
|
||||
#define AXXX_CP_STAT_CP_BUSY 0x80000000
|
||||
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
|
||||
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
|
||||
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
|
||||
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
|
||||
#define AXXX_CP_STAT_ME_BUSY 0x04000000
|
||||
#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
|
||||
#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
|
||||
#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
|
||||
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
|
||||
#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
|
||||
#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
|
||||
#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
|
||||
#define AXXX_CP_STAT_PFP_BUSY 0x00020000
|
||||
#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
|
||||
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
|
||||
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
|
||||
#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
|
||||
#define AXXX_CP_STAT_CSF_BUSY 0x00000400
|
||||
#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
|
||||
#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
|
||||
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
|
||||
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
|
||||
#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
|
||||
#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
|
||||
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
|
||||
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
|
||||
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
|
||||
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
|
||||
|
||||
#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
|
||||
|
||||
#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
|
||||
|
||||
|
||||
#endif /* ADRENO_COMMON_XML */
|
||||
1160
src/freedreno/registers/adreno_pm4.xml
Normal file
1160
src/freedreno/registers/adreno_pm4.xml
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
40
src/freedreno/registers/freedreno_copyright.xml
Normal file
40
src/freedreno/registers/freedreno_copyright.xml
Normal file
@@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<database xmlns="http://nouveau.freedesktop.org/"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||
|
||||
<copyright year="2013">
|
||||
|
||||
<author name="Rob Clark" email="robdclark@gmail.com"><nick name="robclark"/>
|
||||
Initial Author.
|
||||
</author>
|
||||
|
||||
<author name="Ilia Mirkin" email="imirkin@alum.mit.edu"><nick name="imirkin"/>
|
||||
many a3xx/a4xx contributions
|
||||
</author>
|
||||
|
||||
<license>
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
</license>
|
||||
|
||||
</copyright>
|
||||
</database>
|
||||
|
||||
337
src/freedreno/registers/gen_header.py
Normal file
337
src/freedreno/registers/gen_header.py
Normal file
@@ -0,0 +1,337 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
import xml.parsers.expat
|
||||
import sys
|
||||
import os
|
||||
|
||||
class Error(Exception):
|
||||
def __init__(self, message):
|
||||
self.message = message
|
||||
|
||||
class Enum(object):
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.values = []
|
||||
|
||||
def dump(self):
|
||||
prev = 0
|
||||
use_hex = False
|
||||
for (name, value) in self.values:
|
||||
if value > 0x1000:
|
||||
use_hex = True
|
||||
|
||||
print("enum %s {" % self.name)
|
||||
for (name, value) in self.values:
|
||||
if use_hex:
|
||||
print("\t%s = 0x%08x," % (name, value))
|
||||
else:
|
||||
print("\t%s = %d," % (name, value))
|
||||
print("};\n")
|
||||
|
||||
class Field(object):
|
||||
def __init__(self, name, low, high, shr, type, parser):
|
||||
self.name = name
|
||||
self.low = low
|
||||
self.high = high
|
||||
self.shr = shr
|
||||
self.type = type
|
||||
|
||||
builtin_types = [ None, "boolean", "uint", "hex", "int", "fixed", "ufixed", "float" ]
|
||||
|
||||
if low < 0 or low > 31:
|
||||
raise parser.error("low attribute out of range: %d" % low)
|
||||
if high < 0 or high > 31:
|
||||
raise parser.error("high attribute out of range: %d" % high)
|
||||
if high < low:
|
||||
raise parser.error("low is greater than high: low=%d, high=%d" % (low, high))
|
||||
if self.type == "boolean" and not low == high:
|
||||
raise parser.error("booleans should be 1 bit fields");
|
||||
elif self.type == "float" and not (high - low == 31 or high - low == 15):
|
||||
raise parser.error("floats should be 16 or 32 bit fields")
|
||||
elif not self.type in builtin_types and not self.type in parser.enums:
|
||||
raise parser.error("unknown type '%s'" % self.type);
|
||||
|
||||
def ctype(self):
|
||||
if self.type == None:
|
||||
type = "uint32_t"
|
||||
val = "val"
|
||||
elif self.type == "boolean":
|
||||
type = "bool"
|
||||
val = "val"
|
||||
elif self.type == "uint" or self.type == "hex":
|
||||
type = "uint32_t"
|
||||
val = "val"
|
||||
elif self.type == "int":
|
||||
type = "int32_t"
|
||||
val = "val"
|
||||
elif self.type == "fixed":
|
||||
type = "float"
|
||||
val = "((int32_t)(val * %d.0))" % (1 << self.radix)
|
||||
elif self.type == "ufixed":
|
||||
type = "float"
|
||||
val = "((uint32_t)(val * %d.0))" % (1 << self.radix)
|
||||
elif self.type == "float" and self.high - self.low == 31:
|
||||
type = "float"
|
||||
val = "fui(val)"
|
||||
elif self.type == "float" and self.high - self.low == 15:
|
||||
type = "float"
|
||||
val = "util_float_to_half(val)"
|
||||
else:
|
||||
type = "enum %s" % self.type
|
||||
val = "val"
|
||||
|
||||
if self.shr > 0:
|
||||
val = "%s >> %d" % (val, self.shr)
|
||||
|
||||
return (type, val)
|
||||
|
||||
def tab_to(name, value):
|
||||
tab_count = (68 - (len(name) & ~7)) // 8
|
||||
if tab_count == 0:
|
||||
tab_count = 1
|
||||
print(name + ('\t' * tab_count) + value)
|
||||
|
||||
def mask(low, high):
|
||||
return ((0xffffffff >> (32 - (high + 1 - low))) << low)
|
||||
|
||||
class Bitset(object):
|
||||
def __init__(self, name, template):
|
||||
self.name = name
|
||||
self.inline = False
|
||||
if template:
|
||||
self.fields = template.fields
|
||||
else:
|
||||
self.fields = []
|
||||
|
||||
def dump(self, prefix=None):
|
||||
if prefix == None:
|
||||
prefix = self.name
|
||||
for f in self.fields:
|
||||
if f.name:
|
||||
name = prefix + "_" + f.name
|
||||
else:
|
||||
name = prefix
|
||||
|
||||
if not f.name and f.low == 0 and f.shr == 0 and not f.type in ["float", "fixed", "ufixed"]:
|
||||
pass
|
||||
elif f.type == "boolean" or (f.type == None and f.low == f.high):
|
||||
tab_to("#define %s" % name, "0x%08x" % (1 << f.low))
|
||||
else:
|
||||
tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high))
|
||||
tab_to("#define %s__SHIFT" % name, "%d" % f.low)
|
||||
type, val = f.ctype()
|
||||
|
||||
print("static inline uint32_t %s(%s val)\n{" % (name, type))
|
||||
if f.shr > 0:
|
||||
print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1))
|
||||
print("\treturn ((%s) << %s__SHIFT) & %s__MASK;\n}" % (val, name, name))
|
||||
|
||||
class Array(object):
|
||||
def __init__(self, attrs, domain):
|
||||
self.name = attrs["name"]
|
||||
self.domain = domain
|
||||
self.offset = int(attrs["offset"], 0)
|
||||
self.stride = int(attrs["stride"], 0)
|
||||
self.length = int(attrs["length"], 0)
|
||||
|
||||
def dump(self):
|
||||
print("static inline uint32_t REG_%s_%s(uint32_t i0) { return 0x%08x + 0x%x*i0; }\n" % (self.domain, self.name, self.offset, self.stride))
|
||||
|
||||
class Reg(object):
|
||||
def __init__(self, attrs, domain, array):
|
||||
self.name = attrs["name"]
|
||||
self.domain = domain
|
||||
self.array = array
|
||||
self.offset = int(attrs["offset"], 0)
|
||||
self.type = None
|
||||
|
||||
def dump(self):
|
||||
if self.array:
|
||||
name = self.domain + "_" + self.array.name + "_" + self.name
|
||||
offset = self.array.offset + self.offset
|
||||
print("static inline uint32_t REG_%s(uint32_t i0) { return 0x%08x + 0x%x*i0; }" % (name, offset, self.array.stride))
|
||||
else:
|
||||
name = self.domain + "_" + self.name
|
||||
tab_to("#define REG_%s" % name, "0x%08x" % self.offset)
|
||||
|
||||
if self.bitset.inline:
|
||||
self.bitset.dump(name)
|
||||
print("")
|
||||
|
||||
def parse_variants(attrs):
|
||||
if not "variants" in attrs:
|
||||
return None
|
||||
variant = attrs["variants"].split(",")[0]
|
||||
if "-" in variant:
|
||||
variant = variant[:variant.index("-")]
|
||||
|
||||
return variant
|
||||
|
||||
class Parser(object):
|
||||
def __init__(self):
|
||||
self.current_array = None
|
||||
self.current_domain = None
|
||||
self.current_prefix = None
|
||||
self.current_stripe = None
|
||||
self.current_bitset = None
|
||||
self.bitsets = {}
|
||||
self.enums = {}
|
||||
self.file = []
|
||||
|
||||
def error(self, message):
|
||||
parser, filename = self.stack[-1]
|
||||
return Error("%s:%d:%d: %s" % (filename, parser.CurrentLineNumber, parser.CurrentColumnNumber, message))
|
||||
|
||||
def prefix(self):
|
||||
if self.current_stripe:
|
||||
return self.current_stripe + "_" + self.current_domain
|
||||
elif self.current_prefix:
|
||||
return self.current_prefix + "_" + self.current_domain
|
||||
else:
|
||||
return self.current_domain
|
||||
|
||||
def parse_field(self, name, attrs):
|
||||
try:
|
||||
if "pos" in attrs:
|
||||
high = low = int(attrs["pos"], 0)
|
||||
elif "high" in attrs and "low" in attrs:
|
||||
high = int(attrs["high"], 0)
|
||||
low = int(attrs["low"], 0)
|
||||
else:
|
||||
low = 0
|
||||
high = 31
|
||||
|
||||
if "type" in attrs:
|
||||
type = attrs["type"]
|
||||
else:
|
||||
type = None
|
||||
|
||||
if "shr" in attrs:
|
||||
shr = int(attrs["shr"], 0)
|
||||
else:
|
||||
shr = 0
|
||||
|
||||
b = Field(name, low, high, shr, type, self)
|
||||
|
||||
if type == "fixed" or type == "ufixed":
|
||||
b.radix = int(attrs["radix"], 0)
|
||||
|
||||
self.current_bitset.fields.append(b)
|
||||
except ValueError as e:
|
||||
raise self.error(e);
|
||||
|
||||
def do_parse(self, filename):
|
||||
file = open(filename, "rb")
|
||||
parser = xml.parsers.expat.ParserCreate()
|
||||
self.stack.append((parser, filename))
|
||||
parser.StartElementHandler = self.start_element
|
||||
parser.EndElementHandler = self.end_element
|
||||
parser.ParseFile(file)
|
||||
self.stack.pop()
|
||||
file.close()
|
||||
|
||||
def parse(self, filename):
|
||||
self.path = os.path.dirname(filename)
|
||||
self.stack = []
|
||||
self.do_parse(filename)
|
||||
|
||||
def start_element(self, name, attrs):
|
||||
if name == "import":
|
||||
filename = os.path.basename(attrs["file"])
|
||||
self.do_parse(os.path.join(self.path, filename))
|
||||
elif name == "domain":
|
||||
self.current_domain = attrs["name"]
|
||||
if "prefix" in attrs and attrs["prefix"] == "chip":
|
||||
self.current_prefix = parse_variants(attrs)
|
||||
elif name == "stripe":
|
||||
self.current_stripe = parse_variants(attrs)
|
||||
elif name == "enum":
|
||||
self.current_enum_value = 0
|
||||
self.current_enum = Enum(attrs["name"])
|
||||
self.enums[attrs["name"]] = self.current_enum
|
||||
if len(self.stack) == 1:
|
||||
self.file.append(self.current_enum)
|
||||
elif name == "value":
|
||||
if "value" in attrs:
|
||||
value = int(attrs["value"], 0)
|
||||
else:
|
||||
value = self.current_enum_value
|
||||
self.current_enum.values.append((attrs["name"], value))
|
||||
# self.current_enum_value = value + 1
|
||||
elif name == "reg32":
|
||||
if "type" in attrs and attrs["type"] in self.bitsets:
|
||||
self.current_bitset = self.bitsets[attrs["type"]]
|
||||
else:
|
||||
self.current_bitset = Bitset(attrs["name"], None)
|
||||
self.current_bitset.inline = True
|
||||
if "type" in attrs:
|
||||
self.parse_field(None, attrs)
|
||||
|
||||
self.current_reg = Reg(attrs, self.prefix(), self.current_array)
|
||||
self.current_reg.bitset = self.current_bitset
|
||||
|
||||
if len(self.stack) == 1:
|
||||
self.file.append(self.current_reg)
|
||||
elif name == "array":
|
||||
self.current_array = Array(attrs, self.prefix())
|
||||
if len(self.stack) == 1:
|
||||
self.file.append(self.current_array)
|
||||
elif name == "bitset":
|
||||
self.current_bitset = Bitset(attrs["name"], None)
|
||||
if "inline" in attrs and attrs["inline"] == "yes":
|
||||
self.current_bitset.inline = True
|
||||
self.bitsets[self.current_bitset.name] = self.current_bitset
|
||||
if len(self.stack) == 1 and not self.current_bitset.inline:
|
||||
self.file.append(self.current_bitset)
|
||||
elif name == "bitfield" and self.current_bitset:
|
||||
self.parse_field(attrs["name"], attrs)
|
||||
|
||||
def end_element(self, name):
|
||||
if name == "domain":
|
||||
self.current_domain = None
|
||||
self.current_prefix = None
|
||||
elif name == "stripe":
|
||||
self.current_stripe = None
|
||||
elif name == "bitset":
|
||||
self.current_bitset = None
|
||||
elif name == "reg32":
|
||||
self.current_reg = None
|
||||
elif name == "array":
|
||||
self.current_array = None;
|
||||
elif name == "enum":
|
||||
self.current_enum = None
|
||||
|
||||
def dump(self):
|
||||
enums = []
|
||||
bitsets = []
|
||||
regs = []
|
||||
for e in self.file:
|
||||
if isinstance(e, Enum):
|
||||
enums.append(e)
|
||||
elif isinstance(e, Bitset):
|
||||
bitsets.append(e)
|
||||
else:
|
||||
regs.append(e)
|
||||
|
||||
for e in enums + bitsets + regs:
|
||||
e.dump()
|
||||
|
||||
def main():
|
||||
p = Parser()
|
||||
xml_file = sys.argv[1]
|
||||
|
||||
guard = str.replace(os.path.basename(xml_file), '.', '_').upper()
|
||||
print("#ifndef %s\n#define %s\n" % (guard, guard))
|
||||
|
||||
try:
|
||||
p.parse(xml_file)
|
||||
except Error as e:
|
||||
print(e)
|
||||
exit(1)
|
||||
|
||||
p.dump()
|
||||
|
||||
print("\n#endif /* %s */" % guard)
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
41
src/freedreno/registers/meson.build
Normal file
41
src/freedreno/registers/meson.build
Normal file
@@ -0,0 +1,41 @@
|
||||
# Copyright © 2019 Google, Inc
|
||||
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
# SOFTWARE.
|
||||
|
||||
xml_files = [
|
||||
'a2xx.xml',
|
||||
'a3xx.xml',
|
||||
'a4xx.xml',
|
||||
'a5xx.xml',
|
||||
'a6xx.xml',
|
||||
'adreno_common.xml',
|
||||
'adreno_pm4.xml',
|
||||
]
|
||||
|
||||
freedreno_xml_header_files = []
|
||||
foreach f : xml_files
|
||||
_name = f + '.h'
|
||||
freedreno_xml_header_files += custom_target(
|
||||
_name,
|
||||
input : ['gen_header.py', f],
|
||||
output : _name,
|
||||
command : [prog_python, '@INPUT@'],
|
||||
capture : true,
|
||||
)
|
||||
endforeach
|
||||
@@ -86,7 +86,7 @@ endif
|
||||
|
||||
libvulkan_freedreno = shared_library(
|
||||
'vulkan_freedreno',
|
||||
[libtu_files, tu_entrypoints, tu_extensions_c, tu_format_table_c],
|
||||
[libtu_files, tu_entrypoints, tu_extensions_c, tu_format_table_c, freedreno_xml_header_files],
|
||||
include_directories : [
|
||||
inc_common,
|
||||
inc_compiler,
|
||||
|
||||
@@ -729,11 +729,11 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
|
||||
const struct tu_tile *tile)
|
||||
{
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A2XX_CP_SET_MARKER_0_MODE(0x7));
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
|
||||
|
||||
tu6_emit_marker(cmd, cs);
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
|
||||
tu6_emit_marker(cmd, cs);
|
||||
|
||||
const uint32_t x1 = tile->begin.x;
|
||||
@@ -814,7 +814,7 @@ tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
|
||||
|
||||
tu6_emit_marker(cmd, cs);
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
|
||||
tu6_emit_marker(cmd, cs);
|
||||
|
||||
tu6_emit_blit_scissor(cmd, cs);
|
||||
|
||||
@@ -111,7 +111,7 @@ tu_copy_buffer(struct tu_cmd_buffer *cmdbuf,
|
||||
|
||||
/* buffer copy setup */
|
||||
tu_cs_emit_pkt7(&cmdbuf->cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(&cmdbuf->cs, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
tu_cs_emit(&cmdbuf->cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
|
||||
const uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000;
|
||||
|
||||
@@ -356,7 +356,7 @@ tu_copy_buffer_to_image(struct tu_cmd_buffer *cmdbuf,
|
||||
|
||||
/* buffer copy setup */
|
||||
tu_cs_emit_pkt7(&cmdbuf->cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(&cmdbuf->cs, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
tu_cs_emit(&cmdbuf->cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
|
||||
VkFormat format = dst_image->vk_format;
|
||||
const enum a6xx_color_fmt rb_fmt = tu6_get_native_format(format)->rb;
|
||||
@@ -546,7 +546,7 @@ tu_copy_image_to_buffer(struct tu_cmd_buffer *cmdbuf,
|
||||
|
||||
/* buffer copy setup */
|
||||
tu_cs_emit_pkt7(&cmdbuf->cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(&cmdbuf->cs, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
tu_cs_emit(&cmdbuf->cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
|
||||
VkFormat format = src_image->vk_format;
|
||||
const enum a6xx_color_fmt rb_fmt = tu6_get_native_format(format)->rb;
|
||||
|
||||
@@ -255,7 +255,7 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
|
||||
dshift = dbox->x & 0x3f;
|
||||
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
|
||||
uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000;
|
||||
OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
|
||||
@@ -418,7 +418,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
|
||||
uint32_t height = DIV_ROUND_UP(u_minify(src->base.height0, info->src.level), blockheight);
|
||||
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
|
||||
|
||||
uint32_t blit_cntl = blit_control(dfmt);
|
||||
|
||||
|
||||
@@ -158,7 +158,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
|
||||
}
|
||||
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x8));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x8));
|
||||
|
||||
const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size;
|
||||
const unsigned *num_groups = info->grid;
|
||||
|
||||
@@ -262,7 +262,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
|
||||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
OUT_WFI5(ring);
|
||||
@@ -275,7 +275,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
|
||||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0xc));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0xc));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
|
||||
|
||||
@@ -420,7 +420,7 @@ emit_binning_pass(struct fd_batch *batch)
|
||||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
|
||||
@@ -606,7 +606,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
|
||||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
uint32_t x1 = tile->xoff;
|
||||
@@ -1109,7 +1109,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
|
||||
|
||||
if (use_hw_binning(batch)) {
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
|
||||
}
|
||||
|
||||
OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
|
||||
@@ -1124,13 +1124,13 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
|
||||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
fd6_emit_ib(ring, batch->tile_fini);
|
||||
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -1158,7 +1158,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch)
|
||||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
|
||||
|
||||
@@ -232,7 +232,7 @@ endif
|
||||
|
||||
libfreedreno = static_library(
|
||||
'freedreno',
|
||||
[files_libfreedreno],
|
||||
[files_libfreedreno, freedreno_xml_header_files],
|
||||
include_directories : freedreno_includes,
|
||||
c_args : [freedreno_c_args, c_vis_args],
|
||||
cpp_args : [freedreno_cpp_args, cpp_vis_args],
|
||||
|
||||
Reference in New Issue
Block a user