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broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.

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The v3d_qpu_writes_r*() were only checking for fixed-function accumulator
writes, not normal ALU writes to those regs.

Fixes fs-discard-exit-2 on simulation (but not HW).
This commit is contained in:
Eric Anholt
2017-11-07 09:51:56 -08:00
parent 9ccb6621be
commit dfff9ce45e
2 changed files with 33 additions and 5 deletions
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8
src/broadcom/compiler/qpu_schedule.c
View File

@@ -201,13 +201,15 @@ process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
case V3D_QPU_WADDR_R0: case V3D_QPU_WADDR_R0:
case V3D_QPU_WADDR_R1: case V3D_QPU_WADDR_R1:
case V3D_QPU_WADDR_R2: case V3D_QPU_WADDR_R2:
case V3D_QPU_WADDR_R3:
case V3D_QPU_WADDR_R4:
case V3D_QPU_WADDR_R5:
add_write_dep(state, add_write_dep(state,
&state->last_r[waddr - V3D_QPU_WADDR_R0], &state->last_r[waddr - V3D_QPU_WADDR_R0],
n); n);
break; break;
case V3D_QPU_WADDR_R3:
case V3D_QPU_WADDR_R4:
case V3D_QPU_WADDR_R5:
/* Handled by v3d_qpu_writes_r*() checks below. */
break;
case V3D_QPU_WADDR_VPM: case V3D_QPU_WADDR_VPM:
case V3D_QPU_WADDR_VPMU: case V3D_QPU_WADDR_VPMU:

30
src/broadcom/qpu/qpu_instr.c
View File

@@ -602,6 +602,18 @@ v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr)
bool bool
v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst) v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst)
{ {
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
inst->alu.add.waddr == V3D_QPU_WADDR_R3) {
return true;
}
if (inst->alu.mul.magic_write &&
inst->alu.mul.waddr == V3D_QPU_WADDR_R3) {
return true;
}
}
return inst->sig.ldvary || inst->sig.ldvpm; return inst->sig.ldvary || inst->sig.ldvpm;
} }
@@ -613,12 +625,14 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst)
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write && if (inst->alu.add.magic_write &&
v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) { (inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
return true; return true;
} }
if (inst->alu.mul.magic_write && if (inst->alu.mul.magic_write &&
v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) { (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
return true; return true;
} }
} }
@@ -629,6 +643,18 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst)
bool bool
v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst) v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst)
{ {
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
inst->alu.add.waddr == V3D_QPU_WADDR_R5) {
return true;
}
if (inst->alu.mul.magic_write &&
inst->alu.mul.waddr == V3D_QPU_WADDR_R5) {
return true;
}
}
return inst->sig.ldvary || inst->sig.ldunif; return inst->sig.ldvary || inst->sig.ldunif;
} }