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intel/eu: Simplify brw_F32TO16 and brw_F16TO32

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Now that we aren't using them on Gfx8+ we can drop a lot of cruft.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
This commit is contained in:
Kenneth Graunke
2023-03-08 02:05:24 -08:00
committed by Marge Bot
parent c590a3eadf
commit dfe652fb03
2 changed files with 13 additions and 58 deletions
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2
src/intel/compiler/brw_fs_generator.cpp
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@@ -1897,11 +1897,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_ROR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_F32TO16:
assert(devinfo->ver >= 7);
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
assert(devinfo->ver >= 7);
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_CMP: