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radv: fix pipeline caching with robust buffer access

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12900>
This commit is contained in:
Rhys Perry
2021-09-16 15:02:20 +01:00
committed by Marge Bot
parent 5eb59a03ec
commit dfa8ef723b
2 changed files with 6 additions and 0 deletions
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4
src/amd/vulkan/radv_pipeline.c
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@@ -235,6 +235,10 @@ get_hash_flags(const struct radv_device *device, bool stats)
hash_flags |= RADV_HASH_SHADER_FORCE_VRS_2x1;
if (device->force_vrs != RADV_FORCE_VRS_1x2)
hash_flags |= RADV_HASH_SHADER_FORCE_VRS_1x2;
if (device->robust_buffer_access) /* forces per-attribute vertex descriptors */
hash_flags |= RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS;
if (device->robust_buffer_access2) /* affects load/store vectorizer */
hash_flags |= RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS2;
return hash_flags;
}