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etnaviv: Introduce etna_feature enum

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This etna_feature enum will be used as abstraction layer. We will add
support for a hardware database - borrowed from the binary blob.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28574>
This commit is contained in:
Christian Gmeiner
2024-04-01 11:02:01 +02:00
committed by Marge Bot
parent 9eede9ba0b
commit df198d21f9
14 changed files with 272 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
src/etnaviv/common/etna_core_info.h
View File

@@ -7,6 +7,60 @@
#include <stdint.h>
enum etna_feature {
ETNA_FEATURE_FAST_CLEAR,
ETNA_FEATURE_32_BIT_INDICES,
ETNA_FEATURE_MSAA,
ETNA_FEATURE_DXT_TEXTURE_COMPRESSION,
ETNA_FEATURE_ETC1_TEXTURE_COMPRESSION,
ETNA_FEATURE_NO_EARLY_Z,
ETNA_FEATURE_MC20,
ETNA_FEATURE_RENDERTARGET_8K,
ETNA_FEATURE_TEXTURE_8K,
ETNA_FEATURE_HAS_SIGN_FLOOR_CEIL,
ETNA_FEATURE_HAS_SQRT_TRIG,
ETNA_FEATURE_2BITPERTILE,
ETNA_FEATURE_SUPER_TILED,
ETNA_FEATURE_AUTO_DISABLE,
ETNA_FEATURE_TEXTURE_HALIGN,
ETNA_FEATURE_MMU_VERSION,
ETNA_FEATURE_HALF_FLOAT,
ETNA_FEATURE_WIDE_LINE,
ETNA_FEATURE_HALTI0,
ETNA_FEATURE_NON_POWER_OF_TWO,
ETNA_FEATURE_LINEAR_TEXTURE_SUPPORT,
ETNA_FEATURE_LINEAR_PE,
ETNA_FEATURE_SUPERTILED_TEXTURE,
ETNA_FEATURE_LOGIC_OP,
ETNA_FEATURE_HALTI1,
ETNA_FEATURE_SEAMLESS_CUBE_MAP,
ETNA_FEATURE_LINE_LOOP,
ETNA_FEATURE_TEXTURE_TILED_READ,
ETNA_FEATURE_BUG_FIXES8,
ETNA_FEATURE_PE_DITHER_FIX,
ETNA_FEATURE_INSTRUCTION_CACHE,
ETNA_FEATURE_HAS_FAST_TRANSCENDENTALS,
ETNA_FEATURE_SMALL_MSAA,
ETNA_FEATURE_BUG_FIXES18,
ETNA_FEATURE_TEXTURE_ASTC,
ETNA_FEATURE_SINGLE_BUFFER,
ETNA_FEATURE_HALTI2,
ETNA_FEATURE_BLT_ENGINE,
ETNA_FEATURE_HALTI3,
ETNA_FEATURE_HALTI4,
ETNA_FEATURE_HALTI5,
ETNA_FEATURE_RA_WRITE_DEPTH,
ETNA_FEATURE_CACHE128B256BPERLINE,
ETNA_FEATURE_NEW_GPIPE,
ETNA_FEATURE_NO_ASTC,
ETNA_FEATURE_V4_COMPRESSION,
ETNA_FEATURE_RS_NEW_BASEADDR,
ETNA_FEATURE_PE_NO_ALPHA_TEST,
ETNA_FEATURE_SH_NO_ONECONST_LIMIT,
ETNA_FEATURE_DEC400,
ETNA_FEATURE_NUM,
};
struct etna_core_info {
uint32_t model;
uint32_t revision;

5
src/gallium/drivers/etnaviv/etnaviv_blend.c
View File

@@ -29,7 +29,6 @@
#include "etnaviv_context.h"
#include "etnaviv_screen.h"
#include "etnaviv_translate.h"
#include "hw/common.xml.h"
#include "pipe/p_defines.h"
#include "util/u_memory.h"
#include "util/half_float.h"
@@ -93,7 +92,7 @@ etna_blend_state_create(struct pipe_context *pctx,
}
logicop_enable = so->logicop_enable &&
VIV_FEATURE(ctx->screen, chipMinorFeatures2, LOGIC_OP);
VIV_FEATURE(ctx->screen, ETNA_FEATURE_LOGIC_OP);
co->PE_LOGIC_OP =
VIVS_PE_LOGIC_OP_OP(logicop_enable ? so->logicop_func : LOGIC_OP_COPY) |
@@ -110,7 +109,7 @@ etna_blend_state_create(struct pipe_context *pctx,
*/
if (so->dither &&
(!alpha_enable ||
VIV_FEATURE(ctx->screen, chipMinorFeatures3, PE_DITHER_FIX))) {
VIV_FEATURE(ctx->screen, ETNA_FEATURE_PE_DITHER_FIX))) {
co->PE_DITHER[0] = 0x6e4ca280;
co->PE_DITHER[1] = 0x5d7f91b3;
} else {

6
src/gallium/drivers/etnaviv/etnaviv_context.c
View File

@@ -61,8 +61,6 @@
#include "util/u_surface.h"
#include "util/u_transfer.h"
#include "hw/common.xml.h"
static inline void
etna_emit_nop_with_data(struct etna_cmd_stream *stream, uint32_t value)
{
@@ -384,7 +382,7 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
/* First, sync state, then emit DRAW_PRIMITIVES or DRAW_INDEXED_PRIMITIVES */
etna_emit_state(ctx);
if (!VIV_FEATURE(screen, chipMinorFeatures6, NEW_GPIPE)) {
if (!VIV_FEATURE(screen, ETNA_FEATURE_NEW_GPIPE)) {
switch (draw_mode) {
case PRIMITIVE_TYPE_LINE_LOOP:
case PRIMITIVE_TYPE_LINE_STRIP:
@@ -483,7 +481,7 @@ etna_reset_gpu_state(struct etna_context *ctx)
etna_set_state(stream, VIVS_GL_UNK03854, 0x00000000);
}
if (VIV_FEATURE(screen, chipMinorFeatures4, BUG_FIXES18))
if (VIV_FEATURE(screen, ETNA_FEATURE_BUG_FIXES18))
etna_set_state(stream, VIVS_GL_BUG_FIXES, 0x6);
if (!screen->specs.use_blt) {

3
src/gallium/drivers/etnaviv/etnaviv_emit.c
View File

@@ -39,7 +39,6 @@
#include "etnaviv_uniforms.h"
#include "etnaviv_util.h"
#include "etnaviv_zsa.h"
#include "hw/common.xml.h"
#include "hw/state.xml.h"
#include "hw/state_blt.xml.h"
#include "util/u_math.h"
@@ -519,7 +518,7 @@ etna_emit_state(struct etna_context *ctx)
}
}
if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR)) &&
VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT)) {
VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT)) {
/*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.PE_ALPHA_COLOR_EXT0);
/*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.PE_ALPHA_COLOR_EXT1);
}

3
src/gallium/drivers/etnaviv/etnaviv_etc2.c
View File

@@ -28,7 +28,6 @@
#include "etnaviv_etc2.h"
#include "etnaviv_resource.h"
#include "etnaviv_screen.h"
#include "hw/common.xml.h"
#include "util/format/u_format.h"
bool
@@ -39,7 +38,7 @@ etna_etc2_needs_patching(const struct pipe_resource *prsc)
if (!util_format_is_etc(prsc->format))
return false;
if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI1))
return false;
switch (prsc->format) {

4
src/gallium/drivers/etnaviv/etnaviv_rasterizer.c
View File

@@ -25,8 +25,6 @@
#include "etnaviv_context.h"
#include "etnaviv_screen.h"
#include "hw/common.xml.h"
#include "etnaviv_translate.h"
#include "util/u_math.h"
#include "util/u_memory.h"
@@ -52,7 +50,7 @@ etna_rasterizer_state_create(struct pipe_context *pctx,
translate_polygon_mode(so->fill_front) |
COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) |
COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) |
COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE);
COND(VIV_FEATURE(ctx->screen, ETNA_FEATURE_WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE);
cs->PA_LINE_WIDTH = fui(so->line_width / 2.0f);
cs->PA_POINT_SIZE = fui(so->point_size / 2.0f);
cs->SE_DEPTH_SCALE = fui(so->offset_scale);

10
src/gallium/drivers/etnaviv/etnaviv_resource.c
View File

@@ -26,8 +26,6 @@
#include "etnaviv_resource.h"
#include "hw/common.xml.h"
#include "etnaviv_context.h"
#include "etnaviv_debug.h"
#include "etnaviv_screen.h"
@@ -111,7 +109,7 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen,
/* enable 256B ts mode with compression, as it improves performance
* the size of the resource might also determine if we want to use it or not
*/
if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE)) {
if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
if ((modifier & VIVANTE_MOD_TS_MASK) == VIVANTE_MOD_TS_128_4)
ts_mode = TS_MODE_128B;
else if ((modifier & VIVANTE_MOD_TS_MASK) == VIVANTE_MOD_TS_256_4)
@@ -266,7 +264,7 @@ etna_layout_multiple(const struct etna_screen *screen,
* textures. If this GPU uses the BLT engine, never do RS align.
*/
bool rs_align = !specs->use_blt && (!etna_resource_sampler_only(templat) ||
VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN));
VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_HALIGN));
int msaa_xscale = 1, msaa_yscale = 1;
/* Compressed textures are padded to their block size, but we don't have
@@ -435,7 +433,7 @@ etna_resource_create(struct pipe_screen *pscreen,
if (screen->specs.can_supertile)
layout |= ETNA_LAYOUT_BIT_SUPER;
} else if (screen->specs.can_supertile &&
VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE) &&
VIV_FEATURE(screen, ETNA_FEATURE_SUPERTILED_TEXTURE) &&
etna_resource_hw_tileable(screen->specs.use_blt, templat)) {
layout |= ETNA_LAYOUT_BIT_SUPER;
}
@@ -521,7 +519,7 @@ select_best_modifier(const struct etna_screen * screen,
best_modifier = base_modifier = priority_to_modifier[prio];
if (!DBG_ENABLED(ETNA_DBG_SHARED_TS) ||
!VIV_FEATURE(screen, chipFeatures, FAST_CLEAR))
!VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR))
return best_modifier;
/* Make a second pass to try and find the best TS modifier if any. */

15
src/gallium/drivers/etnaviv/etnaviv_rs.c
View File

@@ -45,7 +45,6 @@
#include "util/u_memory.h"
#include "util/u_surface.h"
#include "hw/common.xml.h"
#include "hw/state.xml.h"
#include "hw/state_3d.xml.h"
@@ -106,10 +105,10 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
COND(src_super, VIVS_RS_SOURCE_STRIDE_TILING) |
COND(src_multi, VIVS_RS_SOURCE_STRIDE_MULTI);
if (VIV_FEATURE(ctx->screen, chipMinorFeatures6, CACHE128B256BPERLINE))
if (VIV_FEATURE(ctx->screen, ETNA_FEATURE_CACHE128B256BPERLINE))
cs->RS_SOURCE_STRIDE |= VIVS_RS_SOURCE_STRIDE_TS_MODE(rs->source_ts_mode) |
COND(src_super, VIVS_RS_SOURCE_STRIDE_SUPER_TILED_NEW);
else if ((rs->downsample_x || rs->downsample_y) && VIV_FEATURE(screen, chipMinorFeatures4, SMALL_MSAA))
else if ((rs->downsample_x || rs->downsample_y) && VIV_FEATURE(screen, ETNA_FEATURE_SMALL_MSAA))
cs->RS_SOURCE_STRIDE |= VIVS_RS_SOURCE_STRIDE_TS_MODE(TS_MODE_256B);
/* Initially all pipes are set to the base address of the source and
@@ -132,7 +131,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
COND(dst_super, VIVS_RS_DEST_STRIDE_TILING) |
COND(dst_multi, VIVS_RS_DEST_STRIDE_MULTI);
if (VIV_FEATURE(ctx->screen, chipMinorFeatures6, CACHE128B256BPERLINE))
if (VIV_FEATURE(ctx->screen, ETNA_FEATURE_CACHE128B256BPERLINE))
cs->RS_DEST_STRIDE |= COND(dst_super, VIVS_RS_DEST_STRIDE_SUPER_TILED_NEW);
if (src_multi)
@@ -175,7 +174,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
!rs->swap_rb && !rs->flip &&
!rs->clear_mode && rs->source_padded_width &&
!rs->source_ts_compressed) {
if (VIV_FEATURE(ctx->screen, chipMinorFeatures6, CACHE128B256BPERLINE))
if (VIV_FEATURE(ctx->screen, ETNA_FEATURE_CACHE128B256BPERLINE))
cs->RS_EXTRA_CONFIG |= VIVS_RS_EXTRA_CONFIG_TS_MODE(rs->source_ts_mode);
/* Total number of tiles (same as for autodisable) */
cs->RS_KICKER_INPLACE = rs->tile_count;
@@ -225,7 +224,7 @@ etna_submit_rs_state(struct etna_context *ctx,
/* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE);
etna_coalesce_end(stream, &coalesce);
} else if (screen->specs.pixel_pipes > 1 ||
VIV_FEATURE(screen, chipMinorFeatures7, RS_NEW_BASEADDR)) {
VIV_FEATURE(screen, ETNA_FEATURE_RS_NEW_BASEADDR)) {
etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */
etna_coalesce_start(stream, &coalesce);
/* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
@@ -340,7 +339,7 @@ etna_blit_clear_color_rs(struct pipe_context *pctx, struct pipe_surface *dst,
ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT = new_clear_value >> 32;
if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
if (VIV_FEATURE(ctx->screen, ETNA_FEATURE_AUTO_DISABLE)) {
/* Set number of color tiles to be filled */
etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
surf->level->padded_width * surf->level->padded_height / 16);
@@ -402,7 +401,7 @@ etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst,
if (surf->level->ts_size && new_clear_bits == 0xffff) {
/* Set new clear depth value */
ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
if (VIV_FEATURE(ctx->screen, ETNA_FEATURE_AUTO_DISABLE)) {
/* Set number of depth tiles to be filled */
etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT,
surf->level->padded_width * surf->level->padded_height / 16);

117
src/gallium/drivers/etnaviv/etnaviv_screen.c
View File

@@ -188,10 +188,10 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
case PIPE_CAP_ALPHA_TEST:
return !VIV_FEATURE(screen, chipMinorFeatures7, PE_NO_ALPHA_TEST);
return !VIV_FEATURE(screen, ETNA_FEATURE_PE_NO_ALPHA_TEST);
/* Unsupported features. */
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
@@ -213,12 +213,12 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return screen->specs.stream_count;
case PIPE_CAP_VS_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
/* Texturing. */
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
return VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT);
return VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT);
case PIPE_CAP_TEXTURE_SHADOW_MAP:
return 1;
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
@@ -249,7 +249,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_OCCLUSION_QUERY:
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
/* Preferences */
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
@@ -287,10 +287,10 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
* that there is no support for triangle strips at all. This should
* be refined.
*/
if (VIV_FEATURE(screen, chipMinorFeatures2, BUG_FIXES8))
if (VIV_FEATURE(screen, ETNA_FEATURE_BUG_FIXES8))
modes |= 1 << MESA_PRIM_TRIANGLE_STRIP;
if (VIV_FEATURE(screen, chipMinorFeatures2, LINE_LOOP))
if (VIV_FEATURE(screen, ETNA_FEATURE_LINE_LOOP))
modes |= 1 << MESA_PRIM_LINE_LOOP;
return modes;
@@ -401,7 +401,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
return VIV_FEATURE(screen, ETNA_FEATURE_HAS_SQRT_TRIG);
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_FP16:
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
@@ -467,34 +467,34 @@ gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
return false;
if (fmt == TEXTURE_FORMAT_ETC1)
supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
supported = VIV_FEATURE(screen, ETNA_FEATURE_ETC1_TEXTURE_COMPRESSION);
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
supported = VIV_FEATURE(screen, ETNA_FEATURE_DXT_TEXTURE_COMPRESSION);
if (util_format_is_srgb(format))
supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
if (fmt & EXT_FORMAT)
supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
if (fmt & ASTC_FORMAT) {
supported = screen->specs.tex_astc;
}
if (util_format_is_snorm(format))
supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI1);
if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
(util_format_is_pure_integer(format) || util_format_is_float(format)))
supported = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
if (!supported)
return false;
if (texture_format_needs_swiz(format))
return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
return true;
}
@@ -518,7 +518,7 @@ gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
return false;
/* The hardware supports it. */
if (!VIV_FEATURE(screen, chipFeatures, MSAA))
if (!VIV_FEATURE(screen, ETNA_FEATURE_MSAA))
return false;
/* Number of samples must be allowed. */
@@ -526,7 +526,7 @@ gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
return false;
/* On SMALL_MSAA hardware 2x MSAA does not work. */
if (sample_count == 2 && VIV_FEATURE(screen, chipMinorFeatures4, SMALL_MSAA))
if (sample_count == 2 && VIV_FEATURE(screen, ETNA_FEATURE_SMALL_MSAA))
return false;
/* BLT/RS supports the format. */
@@ -540,24 +540,24 @@ gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
}
if (format == PIPE_FORMAT_R8_UNORM)
return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
/* figure out 8bpp RS clear to enable these formats */
if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT)
return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
if (util_format_is_srgb(format))
return VIV_FEATURE(screen, chipMinorFeatures5, HALTI3);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI3);
if (util_format_is_pure_integer(format) || util_format_is_float(format))
return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
if (format == PIPE_FORMAT_R8G8_UNORM)
return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
/* any other extended format is HALTI0 (only R10G10B10A2?) */
if (fmt >= PE_FORMAT_R16F)
return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
return true;
}
@@ -569,7 +569,7 @@ gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format)
return false;
if (util_format_is_pure_integer(format))
return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
return true;
}
@@ -620,7 +620,7 @@ etna_screen_is_format_supported(struct pipe_screen *pscreen,
/* must be supported index format */
if (format == PIPE_FORMAT_R8_UINT || format == PIPE_FORMAT_R16_UINT ||
(format == PIPE_FORMAT_R32_UINT &&
VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
VIV_FEATURE(screen, ETNA_FEATURE_32_BIT_INDICES))) {
allowed |= PIPE_BIND_INDEX_BUFFER;
}
}
@@ -669,12 +669,12 @@ etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
int i, j;
if (DBG_ENABLED(ETNA_DBG_SHARED_TS) &&
VIV_FEATURE(screen, chipFeatures, FAST_CLEAR)) {
VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR)) {
/* If TS is supported expose the TS modifiers. GPUs with feature
* CACHE128B256BPERLINE have both 128B and 256B color tile TS modes,
* older cores support exactly one TS layout.
*/
if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE))
if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE))
if (screen->specs.v4_compression &&
translate_ts_format(format) != ETNA_NO_MATCH)
mods_multiplier += 4;
@@ -698,8 +698,7 @@ etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
if (j == 0) {
ts_mod = 0;
} else if (VIV_FEATURE(screen, chipMinorFeatures6,
CACHE128B256BPERLINE)) {
} else if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
switch (j) {
case 1:
ts_mod = VIVANTE_MOD_TS_128_4;
@@ -749,10 +748,10 @@ etna_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
return false;
if (ts_mod) {
if (!VIV_FEATURE(screen, chipFeatures, FAST_CLEAR))
if (!VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR))
return false;
if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE)) {
if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
if (ts_mod != VIVANTE_MOD_TS_128_4 &&
ts_mod != VIVANTE_MOD_TS_256_4)
return false;
@@ -933,17 +932,17 @@ etna_get_specs(struct etna_screen *screen)
/* Figure out gross GPU architecture. See rnndb/common.xml for a specific
* description of the differences. */
if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI5))
screen->specs.halti = 5; /* New GC7000/GC8x00 */
else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
else if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI4))
screen->specs.halti = 4; /* Old GC7000/GC7400 */
else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
else if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI3))
screen->specs.halti = 3; /* None? */
else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
else if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI2))
screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
else if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI1))
screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
else if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI0))
screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
else
screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
@@ -953,36 +952,36 @@ etna_get_specs(struct etna_screen *screen)
DBG("etnaviv: GPU arch: pre-HALTI");
screen->specs.can_supertile =
VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
VIV_FEATURE(screen, ETNA_FEATURE_SUPER_TILED);
screen->specs.bits_per_tile =
!VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ||
VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE) ? 4 : 2;
!VIV_FEATURE(screen, ETNA_FEATURE_2BITPERTILE) ||
VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE) ? 4 : 2;
screen->specs.ts_clear_value =
VIV_FEATURE(screen, chipMinorFeatures10, DEC400) ? 0xffffffff :
VIV_FEATURE(screen, ETNA_FEATURE_DEC400) ? 0xffffffff :
screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555;
screen->specs.vs_need_z_div =
screen->info->model < 0x1000 && screen->info->model != 0x880;
screen->specs.has_sin_cos_sqrt =
VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
VIV_FEATURE(screen, ETNA_FEATURE_HAS_SQRT_TRIG);
screen->specs.has_sign_floor_ceil =
VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
VIV_FEATURE(screen, ETNA_FEATURE_HAS_SIGN_FLOOR_CEIL);
screen->specs.has_shader_range_registers =
screen->info->model >= 0x1000 || screen->info->model == 0x880;
screen->specs.npot_tex_any_wrap =
VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
VIV_FEATURE(screen, ETNA_FEATURE_NON_POWER_OF_TWO);
screen->specs.has_new_transcendentals =
VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
VIV_FEATURE(screen, ETNA_FEATURE_HAS_FAST_TRANSCENDENTALS);
screen->specs.has_halti2_instructions =
VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
screen->specs.has_no_oneconst_limit =
VIV_FEATURE(screen, chipMinorFeatures8, SH_NO_ONECONST_LIMIT);
VIV_FEATURE(screen, ETNA_FEATURE_SH_NO_ONECONST_LIMIT);
screen->specs.v4_compression =
VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
VIV_FEATURE(screen, ETNA_FEATURE_V4_COMPRESSION);
screen->specs.seamless_cube_map =
(screen->info->model != 0x880) && /* Seamless cubemap is broken on GC880? */
VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
VIV_FEATURE(screen, ETNA_FEATURE_SEAMLESS_CUBE_MAP);
if (screen->specs.halti >= 5) {
/* GC7000 - this core must load shaders from memory. */
@@ -990,7 +989,7 @@ etna_get_specs(struct etna_screen *screen)
screen->specs.ps_offset = 0;
screen->specs.max_instructions = 0; /* Do not program shaders manually */
screen->specs.has_icache = true;
} else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
} else if (VIV_FEATURE(screen, ETNA_FEATURE_INSTRUCTION_CACHE)) {
/* GC3000 - this core is capable of loading shaders from
* memory. It can also run shaders from registers, as a fallback, but
* "max_instructions" does not have the correct value. It has place for
@@ -1018,7 +1017,7 @@ etna_get_specs(struct etna_screen *screen)
screen->specs.has_icache = false;
}
if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI0)) {
screen->specs.vertex_max_elements = 16;
} else {
/* Etna_viv documentation seems confused over the correct value
@@ -1051,25 +1050,25 @@ etna_get_specs(struct etna_screen *screen)
}
screen->specs.max_texture_size =
VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_8K) ? 8192 : 2048;
screen->specs.max_rendertarget_size =
VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
VIV_FEATURE(screen, ETNA_FEATURE_RENDERTARGET_8K) ? 8192 : 2048;
screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
screen->specs.single_buffer = VIV_FEATURE(screen, ETNA_FEATURE_SINGLE_BUFFER);
if (screen->specs.single_buffer)
DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC) &&
!VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC);
screen->specs.tex_astc = VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_ASTC) &&
!VIV_FEATURE(screen, ETNA_FEATURE_NO_ASTC);
screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
screen->specs.use_blt = VIV_FEATURE(screen, ETNA_FEATURE_BLT_ENGINE);
/* Only allow fast clear with MC2.0 or MMUv2, as the TS unit bypasses the
* memory offset for the MMUv1 linear window on MC1.0 and we have no way to
* fixup the address.
*/
if (!VIV_FEATURE(screen, chipMinorFeatures0, MC20) &&
!VIV_FEATURE(screen, chipMinorFeatures1, MMU_VERSION))
if (!VIV_FEATURE(screen, ETNA_FEATURE_MC20) &&
!VIV_FEATURE(screen, ETNA_FEATURE_MMU_VERSION))
screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
return true;

133
src/gallium/drivers/etnaviv/etnaviv_screen.h
View File

@@ -41,6 +41,7 @@
#include "util/u_helpers.h"
#include "util/u_queue.h"
#include "compiler/nir/nir.h"
#include "hw/common.xml.h"
struct etna_bo;
@@ -64,10 +65,10 @@ enum viv_features_word {
};
/** Convenience macro to probe features from state.xml.h:
* VIV_FEATURE(chipFeatures, FAST_CLEAR)
* VIV_FEATURE(chipMinorFeatures1, AUTO_DISABLE)
* _VIV_FEATURE(chipFeatures, FAST_CLEAR)
* _VIV_FEATURE(chipMinorFeatures1, AUTO_DISABLE)
*/
#define VIV_FEATURE(screen, word, feature) \
#define _VIV_FEATURE(screen, word, feature) \
((screen->features[viv_ ## word] & (word ## _ ## feature)) != 0)
struct etna_screen {
@@ -99,6 +100,128 @@ struct etna_screen {
struct etna_reloc dummy_desc_reloc;
};
static inline bool
VIV_FEATURE(const struct etna_screen *screen, enum etna_feature feature)
{
switch (feature) {
case ETNA_FEATURE_FAST_CLEAR:
return _VIV_FEATURE(screen, chipFeatures, FAST_CLEAR);
case ETNA_FEATURE_32_BIT_INDICES:
return _VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES);
case ETNA_FEATURE_MSAA:
return _VIV_FEATURE(screen, chipFeatures, MSAA);
case ETNA_FEATURE_DXT_TEXTURE_COMPRESSION:
return _VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
case ETNA_FEATURE_ETC1_TEXTURE_COMPRESSION:
return _VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
case ETNA_FEATURE_NO_EARLY_Z:
return _VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z);
case ETNA_FEATURE_MC20:
return _VIV_FEATURE(screen, chipMinorFeatures0, MC20);
case ETNA_FEATURE_RENDERTARGET_8K:
return _VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K);
case ETNA_FEATURE_TEXTURE_8K:
return _VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K);
case ETNA_FEATURE_HAS_SIGN_FLOOR_CEIL:
return _VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
case ETNA_FEATURE_HAS_SQRT_TRIG:
return _VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
case ETNA_FEATURE_2BITPERTILE:
return _VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE);
case ETNA_FEATURE_SUPER_TILED:
return _VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
case ETNA_FEATURE_AUTO_DISABLE:
return _VIV_FEATURE(screen, chipMinorFeatures1, AUTO_DISABLE);
case ETNA_FEATURE_TEXTURE_HALIGN:
return _VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN);
case ETNA_FEATURE_MMU_VERSION:
return _VIV_FEATURE(screen, chipMinorFeatures1, MMU_VERSION);
case ETNA_FEATURE_HALF_FLOAT:
return _VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT);
case ETNA_FEATURE_WIDE_LINE:
return _VIV_FEATURE(screen, chipMinorFeatures1, WIDE_LINE);
case ETNA_FEATURE_HALTI0:
return _VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
case ETNA_FEATURE_NON_POWER_OF_TWO:
return _VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
case ETNA_FEATURE_LINEAR_TEXTURE_SUPPORT:
return _VIV_FEATURE(screen, chipMinorFeatures1, LINEAR_TEXTURE_SUPPORT);
case ETNA_FEATURE_LINEAR_PE:
return _VIV_FEATURE(screen, chipMinorFeatures2, LINEAR_PE);
case ETNA_FEATURE_SUPERTILED_TEXTURE:
return _VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE);
case ETNA_FEATURE_LOGIC_OP:
return _VIV_FEATURE(screen, chipMinorFeatures2, LOGIC_OP);
case ETNA_FEATURE_HALTI1:
return _VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
case ETNA_FEATURE_SEAMLESS_CUBE_MAP:
return _VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
case ETNA_FEATURE_LINE_LOOP:
return _VIV_FEATURE(screen, chipMinorFeatures2, LINE_LOOP);
case ETNA_FEATURE_TEXTURE_TILED_READ:
return _VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ);
case ETNA_FEATURE_BUG_FIXES8:
return _VIV_FEATURE(screen, chipMinorFeatures2, BUG_FIXES8);
case ETNA_FEATURE_PE_DITHER_FIX:
return _VIV_FEATURE(screen, chipMinorFeatures3, PE_DITHER_FIX);
case ETNA_FEATURE_INSTRUCTION_CACHE:
return _VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE);
case ETNA_FEATURE_HAS_FAST_TRANSCENDENTALS:
return _VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
case ETNA_FEATURE_SMALL_MSAA:
return _VIV_FEATURE(screen, chipMinorFeatures4, SMALL_MSAA);
case ETNA_FEATURE_BUG_FIXES18:
return _VIV_FEATURE(screen, chipMinorFeatures4, BUG_FIXES18);
case ETNA_FEATURE_TEXTURE_ASTC:
return _VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
case ETNA_FEATURE_SINGLE_BUFFER:
return _VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
case ETNA_FEATURE_HALTI2:
return _VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
case ETNA_FEATURE_BLT_ENGINE:
return _VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
case ETNA_FEATURE_HALTI3:
return _VIV_FEATURE(screen, chipMinorFeatures5, HALTI3);
case ETNA_FEATURE_HALTI4:
return _VIV_FEATURE(screen, chipMinorFeatures5, HALTI4);
case ETNA_FEATURE_HALTI5:
return _VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
case ETNA_FEATURE_RA_WRITE_DEPTH:
return _VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH);
case ETNA_FEATURE_CACHE128B256BPERLINE:
return _VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE);
case ETNA_FEATURE_NEW_GPIPE:
return _VIV_FEATURE(screen, chipMinorFeatures6, NEW_GPIPE);
case ETNA_FEATURE_NO_ASTC:
return _VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC);
case ETNA_FEATURE_V4_COMPRESSION:
return _VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
case ETNA_FEATURE_RS_NEW_BASEADDR:
return _VIV_FEATURE(screen, chipMinorFeatures7, RS_NEW_BASEADDR);
case ETNA_FEATURE_PE_NO_ALPHA_TEST:
return _VIV_FEATURE(screen, chipMinorFeatures7, PE_NO_ALPHA_TEST);
case ETNA_FEATURE_SH_NO_ONECONST_LIMIT:
return _VIV_FEATURE(screen, chipMinorFeatures8, SH_NO_ONECONST_LIMIT);
case ETNA_FEATURE_DEC400:
return _VIV_FEATURE(screen, chipMinorFeatures10, DEC400);
default:
break;
}
unreachable("invalid feature enum value");
}
static inline struct etna_screen *
etna_screen(struct pipe_screen *pscreen)
{
@@ -117,8 +240,8 @@ static inline size_t
etna_screen_get_tile_size(struct etna_screen *screen, uint8_t ts_mode,
bool is_msaa)
{
if (!VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE)) {
if (VIV_FEATURE(screen, chipMinorFeatures4, SMALL_MSAA) && is_msaa)
if (!VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
if (VIV_FEATURE(screen, ETNA_FEATURE_SMALL_MSAA) && is_msaa)
return 256;
return 64;
}

14
src/gallium/drivers/etnaviv/etnaviv_state.c
View File

@@ -27,8 +27,6 @@
#include "etnaviv_state.h"
#include "hw/common.xml.h"
#include "etnaviv_blend.h"
#include "etnaviv_clear_blit.h"
#include "etnaviv_context.h"
@@ -153,7 +151,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
uint32_t fmt = translate_pe_format(cbuf->base.format);
assert((res->layout & ETNA_LAYOUT_BIT_TILE) ||
VIV_FEATURE(screen, chipMinorFeatures2, LINEAR_PE));
VIV_FEATURE(screen, ETNA_FEATURE_LINEAR_PE));
etna_update_render_surface(pctx, cbuf);
if (res->layout == ETNA_LAYOUT_LINEAR)
@@ -176,7 +174,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
if (nr_samples_color <= 1)
cs->PE_COLOR_FORMAT |= VIVS_PE_COLOR_FORMAT_OVERWRITE;
if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE))
if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE))
cs->PE_COLOR_FORMAT |= COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
/* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
* VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
@@ -366,7 +364,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
cs->RA_CENTROID_TABLE[9] = 0x886688a2;
cs->RA_CENTROID_TABLE[10] = 0x888866aa;
cs->RA_CENTROID_TABLE[11] = 0x668888a6;
if (VIV_FEATURE(screen, chipMinorFeatures4, SMALL_MSAA))
if (VIV_FEATURE(screen, ETNA_FEATURE_SMALL_MSAA))
pe_logic_op |= VIVS_PE_LOGIC_OP_UNK24(0x5);
break;
}
@@ -718,7 +716,7 @@ etna_update_zsa(struct etna_context *ctx)
struct etna_zsa_state *zsa = etna_zsa_state(zsa_state);
struct etna_screen *screen = ctx->screen;
uint32_t new_pe_depth, new_ra_depth;
bool early_z_allowed = !VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z);
bool early_z_allowed = !VIV_FEATURE(screen, ETNA_FEATURE_NO_EARLY_Z);
bool late_zs = false, early_zs = false,
late_z_test = false, early_z_test = false;
@@ -736,7 +734,7 @@ etna_update_zsa(struct etna_context *ctx)
}
if (zsa->z_write_enabled || zsa->stencil_enabled) {
if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) &&
if (VIV_FEATURE(screen, ETNA_FEATURE_RA_WRITE_DEPTH) &&
early_z_allowed &&
!zsa_state->alpha_enabled &&
!shader_state->writes_z &&
@@ -768,7 +766,7 @@ etna_update_zsa(struct etna_context *ctx)
new_ra_depth = 0x0000030 |
COND(early_z_test, VIVS_RA_EARLY_DEPTH_TEST_ENABLE);
if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH)) {
if (VIV_FEATURE(screen, ETNA_FEATURE_RA_WRITE_DEPTH)) {
if (!early_zs)
new_ra_depth |= VIVS_RA_EARLY_DEPTH_WRITE_DISABLE;
/* The new early hierarchical test seems to only work properly if depth

8
src/gallium/drivers/etnaviv/etnaviv_surface.c
View File

@@ -36,8 +36,6 @@
#include "util/u_math.h"
#include "util/u_memory.h"
#include "hw/common.xml.h"
#include "drm-uapi/drm_fourcc.h"
static struct etna_resource *
@@ -57,8 +55,8 @@ etna_render_handle_incompatible(struct pipe_context *pctx,
* and has multi tiling when required.
*/
if ((res->layout != ETNA_LAYOUT_LINEAR ||
(VIV_FEATURE(screen, chipMinorFeatures2, LINEAR_PE) &&
(!VIV_FEATURE(screen, chipFeatures, FAST_CLEAR) ||
(VIV_FEATURE(screen, ETNA_FEATURE_LINEAR_PE) &&
(!VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR) ||
res->levels[level].stride % min_tilesize == 0))) &&
(!need_multitiled || (res->layout & ETNA_LAYOUT_BIT_MULTI)))
return res;
@@ -111,7 +109,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
* indicate the tile status module bypasses the memory
* offset and MMU. */
if (VIV_FEATURE(screen, chipFeatures, FAST_CLEAR) &&
if (VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR) &&
!rsc->ts_bo &&
/* needs to be RS/BLT compatible for transfer_map/unmap */
(rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 &&

10
src/gallium/drivers/etnaviv/etnaviv_texture.c
View File

@@ -26,8 +26,6 @@
#include "etnaviv_texture.h"
#include "hw/common.xml.h"
#include "etnaviv_clear_blit.h"
#include "etnaviv_context.h"
#include "etnaviv_emit.h"
@@ -130,7 +128,7 @@ etna_can_use_sampler_ts(struct pipe_sampler_view *view, int num)
return false;
/* The hardware supports it. */
if (!VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ))
if (!VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_TILED_READ))
return false;
/* The sampler view will be bound to sampler < VIVS_TS_SAMPLER__LEN.
@@ -210,11 +208,11 @@ etna_resource_sampler_compatible(struct etna_resource *res)
struct etna_screen *screen = etna_screen(res->base.screen);
/* This GPU supports texturing from supertiled textures? */
if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE))
if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, ETNA_FEATURE_SUPERTILED_TEXTURE))
return true;
/* This GPU supports texturing from linear textures? */
if (res->layout == ETNA_LAYOUT_LINEAR && VIV_FEATURE(screen, chipMinorFeatures1, LINEAR_TEXTURE_SUPPORT))
if (res->layout == ETNA_LAYOUT_LINEAR && VIV_FEATURE(screen, ETNA_FEATURE_LINEAR_TEXTURE_SUPPORT))
return true;
/* Otherwise, only support tiled layouts */
@@ -222,7 +220,7 @@ etna_resource_sampler_compatible(struct etna_resource *res)
return false;
/* If we have HALIGN support, we can allow for the RS padding */
if (VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN))
if (VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_HALIGN))
return true;
/* Non-HALIGN GPUs only accept 4x4 tile-aligned textures */

4
src/gallium/drivers/etnaviv/etnaviv_zsa.c
View File

@@ -32,8 +32,6 @@
#include "util/half_float.h"
#include "util/u_memory.h"
#include "hw/common.xml.h"
void *
etna_zsa_state_create(struct pipe_context *pctx,
const struct pipe_depth_stencil_alpha_state *so)
@@ -92,7 +90,7 @@ etna_zsa_state_create(struct pipe_context *pctx,
/* calculate extra_reference value */
uint32_t extra_reference = 0;
if (VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT))
if (VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT))
extra_reference = _mesa_float_to_half(SATURATE(so->alpha_ref_value));
cs->PE_STENCIL_CONFIG_EXT =