diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 68380cbedbd..85f02742cc0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4055,6 +4055,11 @@ opt_vectorize_callback(const nir_instr *instr, const void *_)
    if (instr->type != nir_instr_type_alu)
       return 0;
 
+   const struct radv_device *device = _;
+   enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
+   if (chip < GFX9)
+      return 1;
+
    const nir_alu_instr *alu = nir_instr_as_alu(instr);
    const unsigned bit_size = alu->dest.dest.ssa.bit_size;
    if (bit_size != 16)
@@ -4901,7 +4906,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
 
          NIR_PASS(_, stages[i].nir, nir_opt_shrink_vectors);
 
-         NIR_PASS(_, stages[i].nir, nir_lower_alu_to_scalar, NULL, NULL);
+         NIR_PASS(_, stages[i].nir, nir_lower_alu_width, opt_vectorize_callback, device);
 
          /* lower ALU operations */
          NIR_PASS(_, stages[i].nir, nir_lower_int64);
@@ -4967,7 +4972,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
                NIR_PASS(_, stages[i].nir, nir_opt_dce);
             }
 
-            NIR_PASS(_, stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, NULL);
+            NIR_PASS(_, stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, device);
          }
 
          /* cleanup passes */
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7b4fe00556a..15220d2aa1b 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -121,6 +121,20 @@ radv_get_nir_options(struct radv_physical_device *device)
       get_nir_options_for_stage(device, stage);
 }
 
+static uint8_t
+vectorize_vec2_16bit(const nir_instr *instr, const void *_)
+{
+   if (instr->type != nir_instr_type_alu)
+      return 0;
+
+   const nir_alu_instr *alu = nir_instr_as_alu(instr);
+   const unsigned bit_size = alu->dest.dest.ssa.bit_size;
+   if (bit_size == 16)
+      return 2;
+   else
+      return 1;
+}
+
 static bool
 is_meta_shader(nir_shader *nir)
 {
@@ -171,7 +185,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, bool
       NIR_PASS(progress, shader, nir_opt_dead_write_vars);
       NIR_PASS(_, shader, nir_lower_vars_to_ssa);
 
-      NIR_PASS(_, shader, nir_lower_alu_to_scalar, NULL, NULL);
+      NIR_PASS(_, shader, nir_lower_alu_width, vectorize_vec2_16bit, NULL);
       NIR_PASS(_, shader, nir_lower_phis_to_scalar, true);
 
       NIR_PASS(progress, shader, nir_copy_prop);