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anv/cmd_buffer: Use the new emit macro for compute shader dispatch

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Acked-by: Kristian Høgsberg <krh@bitplanet.net>
This commit is contained in:
Jason Ekstrand
2016-04-18 15:11:43 -07:00
parent 06fc7fa684
commit deb13870d8
1 changed files with 62 additions and 50 deletions
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112
src/intel/vulkan/genX_cmd_buffer.c
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@@ -572,17 +572,19 @@ static void
emit_lrm(struct anv_batch *batch, emit_lrm(struct anv_batch *batch,
uint32_t reg, struct anv_bo *bo, uint32_t offset) uint32_t reg, struct anv_bo *bo, uint32_t offset)
{ {
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), anv_batch_emit_blk(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
.RegisterAddress = reg, lrm.RegisterAddress = reg;
.MemoryAddress = { bo, offset }); lrm.MemoryAddress = (struct anv_address) { bo, offset };
}
} }
static void static void
emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm) emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
{ {
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), anv_batch_emit_blk(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
.RegisterOffset = reg, lri.RegisterOffset = reg;
.DataDWord = imm); lri.DataDWord = imm;
}
} }
void genX(CmdDrawIndirect)( void genX(CmdDrawIndirect)(
@@ -695,18 +697,19 @@ void genX(CmdDispatch)(
genX(cmd_buffer_flush_compute_state)(cmd_buffer); genX(cmd_buffer_flush_compute_state)(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER), anv_batch_emit_blk(&cmd_buffer->batch, GENX(GPGPU_WALKER), ggw) {
.SIMDSize = prog_data->simd_size / 16, ggw.SIMDSize = prog_data->simd_size / 16;
.ThreadDepthCounterMaximum = 0, ggw.ThreadDepthCounterMaximum = 0;
.ThreadHeightCounterMaximum = 0, ggw.ThreadHeightCounterMaximum = 0;
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1, ggw.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1;
.ThreadGroupIDXDimension = x, ggw.ThreadGroupIDXDimension = x;
.ThreadGroupIDYDimension = y, ggw.ThreadGroupIDYDimension = y;
.ThreadGroupIDZDimension = z, ggw.ThreadGroupIDZDimension = z;
.RightExecutionMask = pipeline->cs_right_mask, ggw.RightExecutionMask = pipeline->cs_right_mask;
.BottomExecutionMask = 0xffffffff); ggw.BottomExecutionMask = 0xffffffff;
}
anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH)); anv_batch_emit_blk(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH), msf);
} }
#define GPGPU_DISPATCHDIMX 0x2500 #define GPGPU_DISPATCHDIMX 0x2500
@@ -758,48 +761,53 @@ void genX(CmdDispatchIndirect)(
emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 0); emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 0);
/* predicate = (compute_dispatch_indirect_x_size == 0); */ /* predicate = (compute_dispatch_indirect_x_size == 0); */
anv_batch_emit(batch, GENX(MI_PREDICATE), anv_batch_emit_blk(batch, GENX(MI_PREDICATE), mip) {
.LoadOperation = LOAD_LOAD, mip.LoadOperation = LOAD_LOAD;
.CombineOperation = COMBINE_SET, mip.CombineOperation = COMBINE_SET;
.CompareOperation = COMPARE_SRCS_EQUAL); mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
/* Load compute_dispatch_indirect_y_size into SRC0 */ /* Load compute_dispatch_indirect_y_size into SRC0 */
emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 4); emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 4);
/* predicate |= (compute_dispatch_indirect_y_size == 0); */ /* predicate |= (compute_dispatch_indirect_y_size == 0); */
anv_batch_emit(batch, GENX(MI_PREDICATE), anv_batch_emit_blk(batch, GENX(MI_PREDICATE), mip) {
.LoadOperation = LOAD_LOAD, mip.LoadOperation = LOAD_LOAD;
.CombineOperation = COMBINE_OR, mip.CombineOperation = COMBINE_OR;
.CompareOperation = COMPARE_SRCS_EQUAL); mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
/* Load compute_dispatch_indirect_z_size into SRC0 */ /* Load compute_dispatch_indirect_z_size into SRC0 */
emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 8); emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 8);
/* predicate |= (compute_dispatch_indirect_z_size == 0); */ /* predicate |= (compute_dispatch_indirect_z_size == 0); */
anv_batch_emit(batch, GENX(MI_PREDICATE), anv_batch_emit_blk(batch, GENX(MI_PREDICATE), mip) {
.LoadOperation = LOAD_LOAD, mip.LoadOperation = LOAD_LOAD;
.CombineOperation = COMBINE_OR, mip.CombineOperation = COMBINE_OR;
.CompareOperation = COMPARE_SRCS_EQUAL); mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
/* predicate = !predicate; */ /* predicate = !predicate; */
#define COMPARE_FALSE 1 #define COMPARE_FALSE 1
anv_batch_emit(batch, GENX(MI_PREDICATE), anv_batch_emit_blk(batch, GENX(MI_PREDICATE), mip) {
.LoadOperation = LOAD_LOADINV, mip.LoadOperation = LOAD_LOADINV;
.CombineOperation = COMBINE_OR, mip.CombineOperation = COMBINE_OR;
.CompareOperation = COMPARE_FALSE); mip.CompareOperation = COMPARE_FALSE;
}
#endif #endif
anv_batch_emit(batch, GENX(GPGPU_WALKER), anv_batch_emit_blk(batch, GENX(GPGPU_WALKER), ggw) {
.IndirectParameterEnable = true, ggw.IndirectParameterEnable = true;
.PredicateEnable = GEN_GEN <= 7, ggw.PredicateEnable = GEN_GEN <= 7;
.SIMDSize = prog_data->simd_size / 16, ggw.SIMDSize = prog_data->simd_size / 16;
.ThreadDepthCounterMaximum = 0, ggw.ThreadDepthCounterMaximum = 0;
.ThreadHeightCounterMaximum = 0, ggw.ThreadHeightCounterMaximum = 0;
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1, ggw.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1;
.RightExecutionMask = pipeline->cs_right_mask, ggw.RightExecutionMask = pipeline->cs_right_mask;
.BottomExecutionMask = 0xffffffff); ggw.BottomExecutionMask = 0xffffffff;
}
anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH)); anv_batch_emit_blk(batch, GENX(MEDIA_STATE_FLUSH), msf);
} }
static void static void
@@ -817,7 +825,7 @@ flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer,
* hardware too. * hardware too.
*/ */
if (pipeline == GPGPU) if (pipeline == GPGPU)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS)); anv_batch_emit_blk(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
#elif GEN_GEN <= 7 #elif GEN_GEN <= 7
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]": * PIPELINE_SELECT [DevBWR+]":
@@ -853,11 +861,13 @@ genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.current_pipeline != _3D) { if (cmd_buffer->state.current_pipeline != _3D) {
flush_pipeline_before_pipeline_select(cmd_buffer, _3D); flush_pipeline_before_pipeline_select(cmd_buffer, _3D);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), anv_batch_emit_blk(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
#if GEN_GEN >= 9 #if GEN_GEN >= 9
.MaskBits = 3, ps.MaskBits = 3;
#endif #endif
.PipelineSelection = _3D); ps.PipelineSelection = _3D;
}
cmd_buffer->state.current_pipeline = _3D; cmd_buffer->state.current_pipeline = _3D;
} }
} }
@@ -868,11 +878,13 @@ genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.current_pipeline != GPGPU) { if (cmd_buffer->state.current_pipeline != GPGPU) {
flush_pipeline_before_pipeline_select(cmd_buffer, GPGPU); flush_pipeline_before_pipeline_select(cmd_buffer, GPGPU);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), anv_batch_emit_blk(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
#if GEN_GEN >= 9 #if GEN_GEN >= 9
.MaskBits = 3, ps.MaskBits = 3;
#endif #endif
.PipelineSelection = GPGPU); ps.PipelineSelection = GPGPU;
}
cmd_buffer->state.current_pipeline = GPGPU; cmd_buffer->state.current_pipeline = GPGPU;
} }
} }